Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JK

James Karp — 65 Patents

AMD: 63 patents #89 of 9,280Top 1%
RIReliability Incorporated: 1 patents #6 of 12Top 50%
Saratoga, CA: #120 of 2,933 inventorsTop 5%
California: #5,108 of 386,348 inventorsTop 2%
Overall (All Time): #33,516 of 4,157,543Top 1%
65 Patents All Time
James Karp has been granted 65 US patents while listed as an inventor at AMD. The first was granted in 1986 and the most recent in November 2022. James Karp ranks #33,516 of 4,157,543 US inventors in our database (top 0.81%). Patent records list James Karp in Saratoga, CA, US.

Issued Patents All Time

Showing 1–25 of 65 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11508667 Embedded shield for protection of memory cells Yan Wang 2022-11-22
11398469 Electrostatic discharge (ESD) protection in stacked chips 2022-07-26
11177654 Electro-static discharge (ESD) damage self-test John K. Jennings, Michael J. Hart 2021-11-16 $110,062,000
11114429 Integrated circuit device with electrostatic discharge (ESD) protection 2021-09-07 $55,935,000
11043484 Method and apparatus of package enabled ESD protection Hong Shi, Siow Chek Tan, Martin L. Voogel, Mohsen H. Mardi, Suresh Ramalingam +1 more 2021-06-22 $31,440,000
10901097 Method and apparatus for electronics-harmful-radiation (EHR) measurement and monitoring Michael J. Hart 2021-01-26 $142,766,000
10861848 Single event latch-up (SEL) mitigation techniques Michael J. Hart, Mohammed Fakhruddin, Pierre Maillard 2020-12-08 $24,793,000
10811493 Single event latch-up (SEL) mitigation techniques Michael J. Hart 2020-10-20 $35,188,000
10636869 Mitigation for FinFET technology using deep isolation Michael J. Hart 2020-04-28 $32,103,000
10522531 Integrated circuit device and method of transmitting data in an integrated circuit device 2019-12-31 $73,392,000
10497677 ESD protection in a stacked integrated circuit assembly 2019-12-03 $49,935,000
10325901 Circuit for increasing the impedance of an ESD path in an input/output circuit and method of implementing the same Mohammed Fakhruddin 2019-06-18 $134,695,000
10289178 Configurable single event latch-up (SEL) and electrical overvoltage stress (EOS) detection circuit Adrian Lynam, John K. Jennings, Umanath R. Kamath, Michael J. Hart 2019-05-14 $19,001,000
10015916 Removal of electrostatic charges from an interposer via a ground pad thereof for die attach for formation of a stacked die 2018-07-03 $17,103,000
9960227 Removal of electrostatic charges from interposer for die attachment Michael J. Hart 2018-05-01 $29,690,000
9831218 Wafer to wafer stacking Michael J. Hart 2017-11-28 $25,700,000
9607948 Method and circuits for communication in multi-die packages Vassili Kireev 2017-03-28 $9,601,000
9575111 On chip detection of electrical overstress events Michael J. Hart, John K. Jennings 2017-02-21 $30,229,000
9548738 High voltage RC-clamp for electrostatic discharge (ESD) protection 2017-01-17 $33,411,000
9484919 Selection of logic paths for redundancy Praful Jain, Pierre Maillard, Michael J. Hart 2016-11-01 $14,332,000
9483599 Circuit design-specific failure in time rate for single event upsets Praful Jain 2016-11-01 $14,332,000
9462674 Circuits for and methods of providing a charge device model ground path using substrate taps in an integrated circuit device Mohammed Fakhruddin, Kuok-Khian Lo 2016-10-04 $14,677,000
9406738 Inductive structure formed using through silicon vias Vassili Kireev 2016-08-02 $15,645,000
9379109 Integrated circuit having improved radiation immunity Michael J. Hart 2016-06-28 $4,436,000
9378322 Preparing layouts for semiconductor circuits 2016-06-28 $4,436,000