Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12354978 | Coupled loop and void structure integrated in a redistribution layer of a chip package | Po-Wei Chiu, Tzu-No Chen, Li-Sheng Weng, Young-Soo Lee | 2025-07-08 |
| 12136613 | Chip package with near-die integrated passive device | Li-Sheng Weng, Suresh Ramalingam | 2024-11-05 |
| 11950358 | Integrated circuit package with voltage droop mitigation | Frank Lambrecht, Brian D. Philofsky, Prasun K. Raha | 2024-04-02 |
| 11735519 | In-package passive inductive element for reflection mitigation | Zhaoyin D. Wu, Parag Upadhyaya | 2023-08-22 |
| 11688675 | Core cavity noise isolation structure for use in chip packages | Frank Lambrecht, Po-Wei Chiu | 2023-06-27 |
| 11302674 | Modular stacked silicon package assembly | Jaspreet S. Gandhi, Suresh Ramalingam, William E. Allaire, Kerry M. Pierce | 2022-04-12 |
| 11043484 | Method and apparatus of package enabled ESD protection | James Karp, Siow Chek Tan, Martin L. Voogel, Mohsen H. Mardi, Suresh Ramalingam +1 more | 2021-06-22 |
| 10770364 | Chip scale package (CSP) including shim die | Suresh Ramalingam, Siow Chek Tan, Gamal Refai-Ahmed | 2020-09-08 |
| 10314163 | Low crosstalk vertical connection interface | Siow Chek Tan | 2019-06-04 |
| 10057976 | Power-ground co-reference transceiver structure to deliver ultra-low crosstalk | Siow Chek Tan, Sarajuddin Niazi | 2018-08-21 |