DG

Dinesh D. Gaitonde

AM AMD: 20 patents #533 of 9,279Top 6%
MS Monterey Design Systems: 2 patents #12 of 38Top 35%
Motorola: 1 patents #6,475 of 12,470Top 55%
Overall (All Time): #179,663 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12411168 Software defined device variants Matthew H. Klein, Himanshu Verma, Chirag Ravishankar, Maithilee Rajendra KULKARNI 2025-09-09
12079484 Random reads using multi-port memory and on-chip memory blocks Abhishek Jain, Henri Fraisse 2024-09-03
11888693 Time-division multiplexing (TDM) in integrated circuits for routability and runtime enhancement Chirag Ravishankar 2024-01-30
11720255 Random reads using multi-port memory and on-chip memory blocks Abhishek Jain, Henri Fraisse 2023-08-08
11681846 Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs Xiaojian Yang, Frederic Revenu, Amit Gupta 2023-06-20
11263169 Configurable network-on-chip for a programmable device Ian A. Swarbrick, Sagheer Ahmad, Ygal Arbel 2022-03-01
10977404 Dynamic scan chain and method Srinivas T. Reddy, Ritesh Mani 2021-04-13
10838908 Configurable network-on-chip for a programmable device Ian A. Swarbrick, Sagheer Ahmad, Ygal Arbel 2020-11-17
10747929 Resolving timing violations in multi-die circuit designs Henri Fraisse, Chirag Ravishankar 2020-08-18
10628547 Routing circuit designs for implementation using a programmable network on chip Ian A. Swarbrick, Henri Fraisse 2020-04-21
10614191 Performing placement and routing concurrently Henri Fraisse 2020-04-07
10565346 Placement, routing, and deadlock removal for network-on-chip using integer linear programming Vishal Suthar, Amit Gupta, Jinny Singh 2020-02-18
10503861 Placing and routing an interface portion and a main portion of a circuit design Henri Fraisse, Sachin K. Bhutada, Aashish TRIPATHI, Ramakrishna K. Tanikella 2019-12-10
8972920 Re-budgeting connections of a circuit design Grigor S. Gasparyan, Yau-Tsun S. Li 2015-03-03
8937491 Clock network architecture Brian C. Gaide, Steven P. Young, Trevor J. Bauer, Robert M. Ondris 2015-01-20
8667437 Creating a standard cell circuit design from a programmable logic device circuit design Salil Ravindra Raje 2014-03-04
8219957 Global placement legalization for complex packing rules Steven Li 2012-07-10
8024696 Clock speed for a digital circuit Sankaranarayanan Srinivasan 2011-09-20
7886256 Timing analysis of a mapped logic design using physical delays Pradip K. Jha, Yau-Tsun S. Li 2011-02-08
7594212 Automatic pin placement for integrated circuits to aid circuit board design Salil Ravindra Raje 2009-09-22
6775808 Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits Salil Ravindra Raje, Lawrence Pileggi, Olivier Coudert, Padmini Gopalakrishnan, Jackson David Kreiter 2004-08-10
6286128 Method for design optimization using logical and physical information Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li +17 more 2001-09-04
5940779 Architectural power estimation method and apparatus Alberto J. Reyes, Hongyu Xie, Dana Rigg 1999-08-17