Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7418369 | Method and system for efficient implementation of boolean satisfiability | Matthew W. Moskewicz, Conor F. Madigan | 2008-08-26 |
| 6961916 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Feroze P. Taraporevala, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2005-11-01 |
| 6874135 | Method for design validation using retiming | Aarti Gupta, Pranav Ashar | 2005-03-29 |
| 6651234 | Partition-based decision heuristics for SAT and image computation using SAT and BDDs | Aarti Gupta, Zijiang Yang, Pranav Ashar | 2003-11-18 |
| 6449756 | Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design | Lawrence Pileggi, Eric McCaughrin, Abhijeet Chakraborty, Douglas B. Boyle | 2002-09-10 |
| 6442743 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Feroze P. Taraporevala, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2002-08-27 |
| 6367051 | System and method for concurrent buffer insertion and placement of logic gates | Lawrence Pileggi, Emre Tuncer, Abhijeet Chakraborty, Satyamurthy Pullela, Altan Odabasioglu +1 more | 2002-04-02 |
| 6286128 | Method for design optimization using logical and physical information | Lawrence Pileggi, Majid Sarrafzadeh, Abhijeet Chakraborty, Archie Li, Robert E. Shortt +17 more | 2001-09-04 |
| 6247164 | Configurable hardware system implementing Boolean Satisfiability and method thereof | Pranav Ashar, Margaret Martonosi, Peixin Zhong | 2001-06-12 |
| 6192508 | Method for logic optimization for improving timing and congestion during placement in integrated circuit design | Lawrence Pileggi, Abhijeet Chakraborty, Gary K. Yeap, Douglas B. Boyle | 2001-02-20 |
| 6038392 | Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware | Pranav Ashar, Margaret Martonosi, Peixin Zhong | 2000-03-14 |
| 6035109 | Method for using complete-1-distinguishability for FSM equivalence checking | Pranav Ashar, Aarti Gupta | 2000-03-07 |
| 5937183 | Enhanced binary decision diagram-based functional simulation | Pranav Ashar | 1999-08-10 |
| 5841673 | System and method for processing graphic delay data of logic circuit to reduce topological redundancy | Noriya Kobayashi | 1998-11-24 |
| 5522063 | Method of finding minimum-cost feedback-vertex sets for a graph for partial scan testing without exhaustive cycle enumeration | Pranav Ashar | 1996-05-28 |
| 5457638 | Timing analysis of VLSI circuits | Pranav Ashar | 1995-10-10 |
| 5448497 | Exploiting multi-cycle false paths in the performance optimization of sequential circuits | Pranav Ashar, Sujit Dey | 1995-09-05 |