Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332283 | Voltage-variation detection under clock fluctuations | Huachang Xu, Ramprasad Raghavan, Fanny Gur, Manish Harnur | 2025-06-17 |
| 12086516 | Generating integrated circuit floorplans using neural networks | Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean +3 more | 2024-09-10 |
| 11768237 | Leakage screening based on use-case power prediction | Kaushik Balamukundhan, Yiran Li | 2023-09-26 |
| 11675940 | Generating integrated circuit floorplans using neural networks | Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean +3 more | 2023-06-13 |
| 11486911 | Voltage-variation detection under clock fluctuations | Huachang Xu, Ramprasad Raghavan, Fanny Gur, Manish Harnur | 2022-11-01 |
| 11100266 | Generating integrated circuit floorplans using neural networks | Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean +3 more | 2021-08-24 |
| 10699043 | Generating integrated circuit floorplans using neural networks | Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean +3 more | 2020-06-30 |
| 9576098 | Lithography aware leakage analysis | Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi +3 more | 2017-02-21 |
| 8572523 | Lithography aware leakage analysis | Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi +3 more | 2013-10-29 |
| 8572539 | Variability-aware scheme for high-performance asynchronous circuit voltage regulation | Jordi Cortadella, Vigyan Singhal, Luciano Lavagno | 2013-10-29 |
| 8473876 | Lithography aware timing analysis | Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi +3 more | 2013-06-25 |
| 8446224 | Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC | Jordi Cortadella, Luciano Lavagno | 2013-05-21 |
| 7701255 | Variability-aware scheme for asynchronous circuit initialization | Jordi Cortadella, Vigyan Singhal | 2010-04-20 |
| 7458049 | Aggregate sensitivity for statistical static timing analysis | Alessandra Nardi, Srinath R. Naidu, Aliaksandr Antonau | 2008-11-25 |
| 7058907 | Reduction of cross-talk noise in VLSI circuits | Hamid Savoj, Premal Buch | 2006-06-06 |
| 6367051 | System and method for concurrent buffer insertion and placement of logic gates | Lawrence Pileggi, Sharad Malik, Abhijeet Chakraborty, Satyamurthy Pullela, Altan Odabasioglu +1 more | 2002-04-02 |
| 6286128 | Method for design optimization using logical and physical information | Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li +17 more | 2001-09-04 |