Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9576098 | Lithography aware leakage analysis | Emre Tuncer, Hui Zheng, Vivek Raghavan, Amir Ajami, Alessandra Nardi +3 more | 2017-02-21 |
| 8572523 | Lithography aware leakage analysis | Emre Tuncer, Hui Zheng, Vivek Raghavan, Amir Ajami, Alessandra Nardi +3 more | 2013-10-29 |
| 8473876 | Lithography aware timing analysis | Emre Tuncer, Hui Zheng, Vivek Raghavan, Amir Ajami, Alessandra Nardi +3 more | 2013-06-25 |
| 8001493 | Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions | Rajiv V. Joshi | 2011-08-16 |
| 7827514 | Efficient electromagnetic modeling of irregular metal planes | Michael Beattie, Byron L. Krauter, Hui Zheng | 2010-11-02 |
| 7561483 | Internally asymmetric method for evaluating static memory cell dynamic stability | Rajiv V. Joshi, Qiuyi Ye | 2009-07-14 |
| 7558136 | Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability | Rajiv V. Joshi, Qiuyi Ye | 2009-07-07 |
| 7515491 | Method for evaluating leakage effects on static memory cell access time | Rajiv V. Joshi, Qiuyi Ye | 2009-04-07 |
| 7483322 | Ring oscillator row circuit for evaluating memory cell performance | Rajiv V. Joshi, Qiuyi Ye, Yuen H. Chan | 2009-01-27 |
| 7434188 | Lithographically optimized placement tool | Roderick Metcalfe, Vivek Raghavan, Alfred Wong | 2008-10-07 |
| 7376001 | Row circuit ring oscillator method for evaluating memory cell performance | Rajiv V. Joshi, Qiuyi Ye, Yuen H. Chan | 2008-05-20 |
| 7304895 | Bitline variable methods and circuits for evaluating static memory cell dynamic stability | Rajiv V. Joshi, Qiuyi Ye | 2007-12-04 |
| 7301835 | Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability | Rajiv V. Joshi, Qiuyi Ye | 2007-11-27 |
| 7302661 | Efficient electromagnetic modeling of irregular metal planes | Michael Beattie, Byron L. Krauter, Hui Zheng | 2007-11-27 |
| 7137080 | Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit | Emrah Acar, Sani R. Nassif | 2006-11-14 |
| 7134103 | Method, system, and product for verifying voltage drop across an entire integrated circuit package | Michael Beattie, Byron L. Krauter, Hui Zheng | 2006-11-07 |
| 7036104 | Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes | Charles J. Alpert, Steven Thomas Quay | 2006-04-25 |
| 7000205 | Method, apparatus, and program for block-based static timing analysis with uncertainty | Chandramouli V. Kashyap | 2006-02-14 |
| 6968306 | Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model | Charles J. Alpert, Chandramouli V. Kashyap | 2005-11-22 |
| 6950996 | Interconnect delay and slew metrics based on the lognormal distribution | Charles J. Alpert, Chandramouli V. Kashyap, Ying Liu | 2005-09-27 |
| 6868533 | Method and system for extending delay and slew metrics to ramp inputs | Charles J. Alpert, Chandramouli V. Kashyap, Ying Liu | 2005-03-15 |
| 6842714 | Method for determining the leakage power for an integrated circuit | Emrah Acar, Ying Liu, Sani R. Nassif, Haihua Su | 2005-01-11 |
| 6662149 | Method and apparatus for efficient computation of moments in interconnect circuits | Peter R. O'Brien | 2003-12-09 |
| 6434729 | Two moment RC delay metric for performance optimization | Charles J. Alpert, Chandramouli V. Kashyap | 2002-08-13 |
| 6347393 | Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation | Charles J. Alpert, Stephen T. Quay | 2002-02-12 |