Issued Patents All Time
Showing 25 most recent of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10890623 | Power saving scannable latch output driver | William V. Huott, Pradip Patel, Daniel Rodko | 2021-01-12 |
| 10367507 | Dynamic decode circuit with active glitch control | Paul A. Bunce, John D. Davis, Antonio R. Pelella | 2019-07-30 |
| 10320388 | Dynamic decode circuit with active glitch control method | Paul A. Bunce, John D. Davis, Antonio R. Pelella | 2019-06-11 |
| 10312915 | Dynamic decode circuit with active glitch control method | Paul A. Bunce, John D. Davis, Antonio R. Pelella | 2019-06-04 |
| 10312916 | Dynamic decode circuit with delayed precharge | Paul A. Bunce, John D. Davis, Antonio R. Pelella | 2019-06-04 |
| 10224933 | Dynamic decode circuit with active glitch control | Paul A. Bunce, John D. Davis, Antonio R. Pelella | 2019-03-05 |
| 9997218 | Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation | Paul A. Bunce, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2018-06-12 |
| 9966958 | Dynamic decode circuit with active glitch control | Paul A. Bunce, John D. Davis, Antonio R. Pelella | 2018-05-08 |
| 9837142 | Automated stressing and testing of semiconductor memory cells | Michael Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille, Tobias Werner | 2017-12-05 |
| 9805823 | Automated stressing and testing of semiconductor memory cells | Michael Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille, Tobias Werner | 2017-10-31 |
| 9792967 | Managing semiconductor memory array leakage current | Paul A. Bunce, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-10-17 |
| 9786339 | Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation | Paul A. Bunce, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-10-10 |
| 9761289 | Managing semiconductor memory array leakage current | Paul A. Bunce, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-09-12 |
| 9742408 | Dynamic decode circuit with active glitch control | Paul A. Bunce, John D. Davis, Antonio R. Pelella | 2017-08-22 |
| 9711244 | Memory circuit | Silke Penth, David Edward Schmitt, Tobias Werner | 2017-07-18 |
| 9537474 | Transforming a phase-locked-loop generated chip clock signal to a local clock signal | Juergen Pille, Rolf Sautter, Tobias Werner | 2017-01-03 |
| 9401698 | Transforming a phase-locked-loop generated chip clock signal to a local clock signal | Juergen Pille, Rolf Sautter, Tobias Werner | 2016-07-26 |
| 9355692 | High frequency write through memory device | Paul A. Bunce, John D. Davis, Diana M. Henderson, Jigar Vora | 2016-05-31 |
| 9281024 | Write/read priority blocking scheme using parallel static address decode path | Paul A. Bunce, John D. Davis, Diana M. Henderson | 2016-03-08 |
| 9281025 | Write/read priority blocking scheme using parallel static address decode path | Paul A. Bunce, John D. Davis, Diana M. Henderson | 2016-03-08 |
| 9070433 | SRAM supply voltage global bitline precharge pulse | Paul A. Bunce, John D. Davis, Diana M. Henderson | 2015-06-30 |
| 8837235 | Local evaluation circuit for static random-access memory | Michael Kugel, Silke Penth, Tobias Werner | 2014-09-16 |
| 8587990 | Global bit line restore by most significant bit of an address line | Michael Kugel, Raphael Polig, Tobias Werner | 2013-11-19 |
| 8339893 | Dual beta ratio SRAM | Louis C. Hsu, Xu Ouyang, Robert C. Wong | 2012-12-25 |
| 8325543 | Global bit select circuit interface with false write through blocking | Antonia R. Pelella | 2012-12-04 |