Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12190078 | Rounding hexadecimal floating point numbers using binary incrementors | Michael Klein, Petra Leber, Cedric Lichtenau, Kerstin Claudia Schelm | 2025-01-07 |
| 12056465 | Verifying the correctness of a leading zero counter | Michael Klein, Petra Leber, Cedric Lichtenau, Kerstin Claudia Schelm | 2024-08-06 |
| 11817697 | Method to limit the time a semiconductor device operates above a maximum operating voltage | Adam B. Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi +9 more | 2023-11-14 |
| 11663270 | Vector string search instruction | Cedric Lichtenau, Jonathan D. Bradbury, Eric M. Schwarz, Razvan Peter Figuli | 2023-05-30 |
| 11531546 | Hexadecimal floating point multiply and add instruction | Eric M. Schwarz, Petra Leber, Kerstin Claudia Schelm, Michael Klein, Timothy J. Slegel +2 more | 2022-12-20 |
| 11256511 | Instruction scheduling during execution in a processor | Cedric Lichtenau, Kerstin Claudia Schelm, Anthony Saporito, Gregory W. Alexander | 2022-02-22 |
| 11221826 | Parallel rounding for conversion from binary floating point to binary coded decimal | Silvia M. Mueller, Razvan Peter Figuli, Revital Arieli | 2022-01-11 |
| 11210064 | Parallelized rounding for decimal floating point to binary coded decimal conversion | Silvia M. Mueller, Nicol Hofmann, Razvan Peter Figuli | 2021-12-28 |
| 11175921 | Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback | Juergen Haess, Cedric Lichtenau, Kerstin Claudia Schelm | 2021-11-16 |
| 11099602 | Fault-tolerant clock gating | Razvan Peter Figuli, Cedric Lichtenau, Michael Klein | 2021-08-24 |
| 11068541 | Vector string search instruction | Cedric Lichtenau, Jonathan D. Bradbury, Eric M. Schwarz, Razvan Peter Figuli | 2021-07-20 |
| 11042371 | Plausability-driven fault detection in result logic and condition codes for fast exact substring match | Razvan Peter Figuli, Cedric Lichtenau, Kerstin Claudia Schelm | 2021-06-22 |
| 10996951 | Plausibility-driven fault detection in string termination logic for fast exact substring match | Razvan Peter Figuli, Petra Leber, Cedric Lichtenau | 2021-05-04 |
| 10983159 | Method and apparatus for wiring multiple technology evaluation circuits | Michael Klein, Cedric Lichtenau, Ralf Richter | 2021-04-20 |
| 10890622 | Integrated circuit control latch protection | Michael Klein, Nicol Hofmann, Cedric Lichtenau | 2021-01-12 |
| 10782968 | Rapid substring detection within a data element string | Razvan Peter Figuli, Cedric Lichtenau, Kerstin Claudia Schelm | 2020-09-22 |
| 10747819 | Rapid partial substring matching | Razvan Peter Figuli, Cedric Lichtenau, Nicol Hofmann | 2020-08-18 |
| 10732972 | Non-overlapping substring detection within a data element string | Razvan Peter Figuli, Cedric Lichtenau, Petra Leber | 2020-08-04 |
| 10552167 | Clock-gating for multicycle instructions | Juergen Haess, Cedric Lichtenau, Kerstin Claudia Schelm | 2020-02-04 |
| 10169451 | Rapid character substring searching | Razvan Peter Figuli, Cedric Lichtenau, Michael Klein | 2019-01-01 |
| 9977680 | Clock-gating for multicycle instructions | Juergen Haess, Cedric Lichtenau, Kerstin Claudia Schelm | 2018-05-22 |
| 9837142 | Automated stressing and testing of semiconductor memory cells | Yuen H. Chan, Michael Kugel, Wolfgang Penth, Juergen Pille, Tobias Werner | 2017-12-05 |
| 9805823 | Automated stressing and testing of semiconductor memory cells | Yuen H. Chan, Michael Kugel, Wolfgang Penth, Juergen Pille, Tobias Werner | 2017-10-31 |
| 9715944 | Automatic built-in self test for memory arrays | Lior Binyamini, Wolfgang Penth, Ido Rozenberg | 2017-07-25 |
| 9704567 | Stressing and testing semiconductor memory cells | Michael Kugel, Wolfgang Penth, Juergen Pille | 2017-07-11 |