Issued Patents All Time
Showing 25 most recent of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12260159 | System for collaborative hardware RTL logic timing debug in integrated circuit designs | Arun Joseph, Wolfgang Roesner, Shashidhar Reddy, Sampath Goud Baddam, Matthias Klein | 2025-03-25 |
| 12141076 | Translation support for a virtual cache | Markus Helms, Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart +1 more | 2024-11-12 |
| 12008395 | Program event recording storage alteration processing for a neural network accelerator instruction | Simon Weishaupt, Timothy J. Slegel | 2024-06-11 |
| 11892949 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Aaron Tsai | 2024-02-06 |
| 11817697 | Method to limit the time a semiconductor device operates above a maximum operating voltage | Adam B. Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi +9 more | 2023-11-14 |
| 11775445 | Translation support for a virtual cache | Markus Helms, Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart +1 more | 2023-10-03 |
| 11693692 | Program event recording storage alteration processing for a neural network accelerator instruction | Simon Weishaupt, Timothy J. Slegel | 2023-07-04 |
| 11675899 | Hardware mitigation for Spectre and meltdown-like attacks | Christian Borntraeger, Jonathan D. Bradbury, Martin Recktenwald | 2023-06-13 |
| 11669331 | Neural network processing assist instruction | Laith M. AlBarakat, Jonathan D. Bradbury, Timothy J. Slegel, Cedric Lichtenau, Simon Weishaupt | 2023-06-06 |
| 11645193 | Heterogeneous services for enabling collaborative logic design and debug in aspect oriented hardware designing | Arun Joseph, Wolfgang Roesner, Matthias Klein, Sampath Goud Baddam, Shashidhar Reddy | 2023-05-09 |
| 11586542 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Aaron Tsai | 2023-02-21 |
| 11403222 | Cache structure using a logical directory | Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Aaron Tsai | 2022-08-02 |
| 11366759 | Temporarily suppressing processing of a restrained storage operand request | Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Donald W. Schmidt, Chung-Lung K. Shum | 2022-06-21 |
| 11256511 | Instruction scheduling during execution in a processor | Cedric Lichtenau, Stefan Payer, Kerstin Claudia Schelm, Gregory W. Alexander | 2022-02-22 |
| 11243774 | Dynamic selection of OSC hazard avoidance mechanism | James R. Cuffney, Adam B. Collura, James J. Bonanno, Edward T. Malley, Jang-Soo Lee +2 more | 2022-02-08 |
| 11182165 | Skip-over offset branch prediction | James J. Bonanno, Daniel Lipetz, Brian R. Prasky, Adam B. Collura, Steven J. Hnatko | 2021-11-23 |
| 11182293 | Operating different processor cache levels | Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer | 2021-11-23 |
| 11175923 | Comparing load instruction address fields to store instruction address fields in a table to delay issuing dependent load instructions | Gregory W. Alexander, James J. Bonanno, Adam B. Collura, Bruce C. Giamei, Christian Jacobi +3 more | 2021-11-16 |
| 11169922 | Method and arrangement for saving cache power | Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Siegmund Schlechter | 2021-11-09 |
| 11163573 | Hierarchical metadata predictor with periodic updates | James J. Bonanno, Varnika Atmakuri, Adam B. Collura, Brian R. Prasky, Suman Amugothu | 2021-11-02 |
| 11113055 | Store instruction to store instruction dependency | Edward T. Malley, Jang-Soo Lee, Chung-Lung K. Shum, Gregory W. Alexander | 2021-09-07 |
| 11080052 | Determining the effectiveness of prefetch instructions | Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum, Timothy J. Slegel | 2021-08-03 |
| 11010298 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Aaron Tsai | 2021-05-18 |
| 11010168 | Effectiveness and prioritization of prefetches | Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum | 2021-05-18 |
| 11010066 | Identifying processor attributes based on detecting a guarded storage event | Dan F. Greiner, Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Timothy J. Slegel | 2021-05-18 |