Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11182165 | Skip-over offset branch prediction | James J. Bonanno, Daniel Lipetz, Brian R. Prasky, Anthony Saporito, Adam B. Collura | 2021-11-23 |
| 10990405 | Call/return stack branch target predictor to multiple next sequential instruction addresses | Adam B. Collura, James J. Bonanno, Brian R. Prasky, Daniel Lipetz | 2021-04-27 |
| 10585858 | Log synchronization among discrete devices in a computer system | Thomas J. Griffin | 2020-03-10 |
| 10223372 | Log synchronization among discrete devices in a computer system | Thomas J. Griffin | 2019-03-05 |
| 9934863 | Dynamically adjusting read voltage in a NAND flash memory | Thomas J. Griffin | 2018-04-03 |
| 9934865 | Dynamically adjusting read voltage in a NAND flash memory | Thomas J. Griffin | 2018-04-03 |
| 9691488 | Dynamically adjusting read voltage in a NAND flash memory | Thomas J. Griffin | 2017-06-27 |
| 9659664 | Dynamically adjusting read voltage in a NAND flash memory | Thomas J. Griffin | 2017-05-23 |
| 8874808 | Hierarchical buffer system enabling precise data delivery through an asynchronous boundary | Gary A. Van Huben | 2014-10-28 |
| 8775904 | Efficient storage of meta-bits within a system memory | John Steven Dodson, Benjiman L. Goodman, Kenneth L. Wright | 2014-07-08 |
| 8775906 | Efficient storage of meta-bits within a system memory | John Steven Dodson, Benjiman L. Goodman, Kenneth L. Wright | 2014-07-08 |
| 8635390 | System and method for a hierarchical buffer system for a shared data bus | Gary A. Van Huben | 2014-01-21 |
| 7290159 | Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies | Kirk D. Lamb, Kevin C. Gower, Thomas J. Griffin, Dustin J. VanStee | 2007-10-30 |