KG

Kevin C. Gower

IBM: 138 patents #337 of 70,183Top 1%
HI Hitachi: 1 patents #17,742 of 28,497Top 65%
Overall (All Time): #7,400 of 4,157,543Top 1%
138
Patents All Time

Issued Patents All Time

Showing 25 most recent of 138 patents

Patent #TitleCo-InventorsDate
9325534 Configurable differential to single ended IO Frank D. Ferraiolo, Robert B. Tremaine, Kenneth L. Wright 2016-04-26
8898511 Homogeneous recovery in a redundant memory system Luis A. Lastras-Montano, Patrick J. Meaney, Vesselina K. Papazova, Eldee Stephens 2014-11-25
8862944 Isolation of faulty links in a transmission medium John Steven Dodson, Frank D. Ferraiolo, Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano +1 more 2014-10-14
8856579 Memory interface having extended strobe burst for read timing calibration Kyu-hyoun Kim 2014-10-07
8775858 Heterogeneous recovery in a redundant memory system Luis A. Lastras-Montano, Patrick J. Meaney, Vesselina K. Papazova, Eldee Stephens 2014-07-08
8769335 Homogeneous recovery in a redundant memory system Luis A. Lastras-Montano, Patrick J. Meaney, Vesselina K. Papazova, Eldee Stephens 2014-07-01
8659959 Advanced memory device having improved performance, reduced power and increased reliability Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Hillery C. Hunter +2 more 2014-02-25
8639874 Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device Warren E. Maule, Kyu-hyoun Kim, Dustin J. VanStee 2014-01-28
8635487 Memory interface having extended strobe burst for write timing calibration Kyu-hyoun Kim 2014-01-21
8631271 Heterogeneous recovery in a redundant memory system Lisa C. Gower, Luis A. Lastras-Montano, Patrick J. Meaney, Vesselina K. Papazova, Eldee Stephens 2014-01-14
8589769 System, method and storage medium for providing fault detection and correction in a memory subsystem Timothy J. Dell, Warren E. Maule 2013-11-19
8566682 Failing bus lane detection using syndrome analysis Luis A. Lastras-Montano, Patrick J. Meaney 2013-10-22
8516338 Error correcting code protected quasi-static bit communication on a high-speed bus Peter Buchmann, Robert J. Reese, Martin Schmatz, Michael R. Trombley 2013-08-20
8493801 Strobe offset in bidirectional memory strobe configurations Daniel M. Dreps, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman +3 more 2013-07-23
8495328 Providing frame start indication in a memory system having indeterminate read data latency Paul W. Coteus, Warren E. Maule, Robert B. Tremaine 2013-07-23
8489936 High reliability memory module with a fault tolerant address and command bus Bruce G. Hazelzet, Mark W. Kellogg, David J. Perlman 2013-07-16
8484529 Error correction and detection in a redundant memory system Luiz C. Alves, Luis A. Lastras-Montano, Patrick J. Meaney, Eldee Stephens 2013-07-09
8452919 Advanced memory device having improved performance, reduced power and increased reliability Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Hillery C. Hunter +2 more 2013-05-28
8379459 Memory system with delay locked loop (DLL) bypass control Kyu-hyoun Kim, Warren E. Maule 2013-02-19
8327105 Providing frame start indication in a memory system having indeterminate read data latency Paul W. Coteus, Warren E. Maule, Robert B. Tremaine 2012-12-04
8307270 Advanced memory device having improved performance, reduced power and increased reliability Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Hillery C. Hunter +2 more 2012-11-06
8296541 Memory subsystem with positional read data latency Kevin W. Kark, Mark W. Kellogg, Warren E. Maule 2012-10-23
8289798 Voltage regulator bypass in memory device Paul W. Coteus, Kyu-hyoun Kim 2012-10-16
8284621 Strobe offset in bidirectional memory strobe configurations Daniel M. Dreps, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman +3 more 2012-10-09
8245105 Cascade interconnect memory system with enhanced reliability Timothy J. Dell, Warren E. Maule, Michael R. Trombley 2012-08-14