Issued Patents All Time
Showing 51–75 of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7899983 | Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module | Warren E. Maule | 2011-03-01 |
| 7895374 | Dynamic segment sparing and repair in a memory system | Frank D. Ferraiolo, Ravi Kumar Arimilli, Daniel M. Dreps, Robert J. Reese | 2011-02-22 |
| 7890676 | Memory systems for automated computing machinery | Daniel M. Dreps, Warren E. Maule, Robert B. Tremaine | 2011-02-15 |
| 7863091 | Planar array contact memory cards | Paul W. Coteus, Shawn A. Hall, Gareth G. Hougham, Dale J. Pearson | 2011-01-04 |
| 7865674 | System for enhancing the memory bandwidth available through a memory module | Warren E. Maule | 2011-01-04 |
| 7863089 | Planar array contact memory cards | Paul W. Coteus, Shawn A. Hall, Gareth G. Hougham, Dale J. Pearson | 2011-01-04 |
| 7861014 | System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel | Warren E. Maule | 2010-12-28 |
| 7844771 | System, method and storage medium for a memory subsystem command interface | Warren E. Maule | 2010-11-30 |
| 7840748 | Buffered memory module with multiple memory device data interface ports supporting double the memory capacity | Warren E. Maule | 2010-11-23 |
| 7818497 | Buffered memory module supporting two independent memory channels | Warren E. Maule | 2010-10-19 |
| 7793143 | Switching a defective signal line with a spare signal line without shutting down the computer system | Edgar R. Cordero, James Stephen Fields, Jr., Eric E. Retter | 2010-09-07 |
| 7770077 | Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem | Ravi Kumar Arimilli, Warren E. Maule | 2010-08-03 |
| 7765368 | System, method and storage medium for providing a serialized memory interface with a bus repeater | Kevin W. Kark, Mark W. Kellogg, Warren E. Maule | 2010-07-27 |
| 7761771 | High reliability memory module with a fault tolerant address and command bus | Bruce G. Hazelzet, Mark W. Kellogg, David J. Perlman | 2010-07-20 |
| 7739633 | Verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling system and program product | Faisal Ahmad, Anish Patel | 2010-06-15 |
| 7729153 | 276-pin buffered memory module with enhanced fault tolerance | Daniel M. Dreps, Frank D. Ferraiolo, Mark W. Kellogg, Roger A. Rippens | 2010-06-01 |
| 7717752 | 276-pin buffered memory module with enhanced memory system interconnect and features | Karl D. Loughner, Charles A. Kilmer, Warren E. Maule | 2010-05-18 |
| 7707452 | Recovering from errors in a data processing system | Edgar R. Cordero, James Stephen Fields, Jr., Eric E. Retter, Scott Barnett Swaney | 2010-04-27 |
| 7685392 | Providing indeterminate read data latency in a memory system | Paul W. Coteus, Warren E. Maule, Robert B. Tremaine | 2010-03-23 |
| 7669086 | Systems and methods for providing collision detection in a memory system | Thomas J. Griffin, Dustin J. VanStee | 2010-02-23 |
| 7627732 | Memory systems for automated computing machinery | Paul W. Coteus, Robert B. Tremaine | 2009-12-01 |
| 7624245 | Memory systems for automated computing machinery | Paul W. Coteus, Robert B. Tremaine | 2009-11-24 |
| 7624244 | System for providing a slow command decode over an untrained high-speed interface | ChiWei Yung | 2009-11-24 |
| 7624225 | System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system | Thomas J. Griffin, Kirk D. Lamb, Dustin J. VanStee | 2009-11-24 |
| 7617367 | Memory system including a two-on-one link memory subsystem interconnection | John E. Campbell | 2009-11-10 |