DP

David J. Perlman

IBM: 18 patents #6,125 of 70,183Top 9%
Overall (All Time): #258,231 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8489936 High reliability memory module with a fault tolerant address and command bus Kevin C. Gower, Bruce G. Hazelzet, Mark W. Kellogg 2013-07-16
7761771 High reliability memory module with a fault tolerant address and command bus Kevin C. Gower, Bruce G. Hazelzet, Mark W. Kellogg 2010-07-20
7363533 High reliability memory module with a fault tolerant address and command bus Kevin C. Gower, Bruce G. Hazelzet, Mark W. Kellogg 2008-04-22
7234099 High reliability memory module with a fault tolerant address and command bus Kevin C. Gower, Bruce G. Hazelzet, Mark W. Kellogg 2007-06-19
5923181 Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module Kenneth E. Beilstein, Jr., Claude L. Bertin, Dennis Charles Dubois, Wayne J. Howell, Gordon A. Kelley, Jr. +4 more 1999-07-13
5786628 Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging Kenneth E. Beilstein, Jr., Claude L. Bertin, John Cronin, Wayne J. Howell, James M. Leas 1998-07-28
5719438 Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging Kenneth E. Beilstein, Jr., Claude L. Bertin, John Cronin, Wayne J. Howell, James M. Leas 1998-02-17
5712190 Process for controlling distance between integrated circuit chips in an electronic module Claude L. Bertin, John Cronin 1998-01-27
5686843 Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module Kenneth E. Beilstein, Jr., Claude L. Bertin, Dennis Charles Dubois, Wayne J. Howell, Gordon A. Kelley, Jr. +4 more 1997-11-11
5567653 Process for aligning etch masks on an integrated circuit surface using electromagnetic energy Claude L. Bertin, John Cronin 1996-10-22
5567654 Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging Kenneth E. Beilstein, Jr., Claude L. Bertin, John Cronin, Wayne J. Howell, James M. Leas 1996-10-22
5532519 Cube wireability enhancement with chip-to-chip alignment and thickness control Claude L. Bertin, John Cronin 1996-07-02
5478781 Polyimide-insulated cube package of stacked semiconductor device chips Claude L. Bertin, Paul A. Farrar, Wayne J. Howell, Christopher P. Miller 1995-12-26
5414637 Intra-module spare routing for high density electronic packages Claude L. Bertin, Christopher P. Miller 1995-05-09
5297091 Early row address strobe (RAS) precharge Robert M. Blake, William Paul Hovis 1994-03-22
5229639 Low powder distribution inductance lead frame for semiconductor chips Kenneth M. Hansen 1993-07-20
4341942 Method of bonding wires to passivated chip microcircuit conductors Praveen Chaudhari, John B. Kiessling, Eugene E. Tynan, Robert J. von Gutfeld 1982-07-27
4196389 Test site for a charged coupled device (CCD) array Helen J. Kelly, Akella V. S. Satya 1980-04-01