Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11557342 | Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array | Nanbo Gong, Wei-Chih Chien, Matthew J. BrightSky, Hsiang-Lan Lung | 2023-01-17 |
| 11139025 | Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array | Nanbo Gong, Wei-Chih Chien, Matthew J. BrightSky, Hsiang-Lan Lung | 2021-10-05 |
| 9760106 | Integrated circuit having regulated voltage island power system | Donald W. Labrecque, Steffen Loeffler, Christopher Scoville | 2017-09-12 |
| 9335775 | Integrated circuit having regulated voltage island power system | Donald W. Labrecque, Steffen Loeffler, Christopher Scoville | 2016-05-10 |
| 6446163 | Memory card with signal processing element | Bruce G. Hazelzet, Clarence R. Ogilvie, Paul C. Stabler | 2002-09-03 |
| 6429730 | Bias circuit for series connected decoupling capacitors | Russell J. Houghton | 2002-08-06 |
| 6347058 | Sense amplifier with overdrive and regulated bitline voltage | Russell J. Houghton | 2002-02-12 |
| 6327664 | Power management on a memory card having a signal processing element | Timothy J. Dell, Bruce G. Hazelzet, Mark W. Kellogg | 2001-12-04 |
| 6271717 | Bias circuit for series connected decoupling capacitors | Russell J. Houghton | 2001-08-07 |
| 6268748 | Module with low leakage driver circuits and method of operation | Claude L. Bertin, John A. Fifield, Russell J. Houghton, William R. Tonti | 2001-07-31 |
| 6204723 | Bias circuit for series connected decoupling capacitors | Russell J. Houghton | 2001-03-20 |
| 6195027 | Capacitive precharging and discharging network for converting N bit input into M bit output | Claude L. Bertin, John A. Fifield, Russell J. Houghton, Steven W. Tomashot, William R. Tonti | 2001-02-27 |
| 6166561 | Method and apparatus for protecting off chip driver circuitry employing a split rail power supply | John A. Fifield | 2000-12-26 |
| 5987577 | Dual word enable method and apparatus for memory arrays | Mark A. Beiley | 1999-11-16 |
| 5923181 | Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module | Kenneth E. Beilstein, Jr., Claude L. Bertin, Dennis Charles Dubois, Wayne J. Howell, Gordon A. Kelley, Jr. +4 more | 1999-07-13 |
| 5909400 | Three device BICMOS gain cell | Claude L. Bertin, John A. Fifield, Russell J. Houghton, William R. Tonti | 1999-06-01 |
| 5880988 | Reference potential for sensing data in electronic storage element | Claude L. Bertin, John A. Fifield, Russell J. Houghton, William R. Tonti | 1999-03-09 |
| 5809528 | Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory | Dale E. Pontius | 1998-09-15 |
| 5787457 | Cached synchronous DRAM architecture allowing concurrent DRAM operations | Jim L. Rogers, Steven W. Tomashot | 1998-07-28 |
| 5761114 | Multi-level storage gain cell with stepline | Claude L. Bertin, John A. Fifield, Russell J. Houghton, William R. Tonti | 1998-06-02 |
| 5757693 | Gain memory cell with diode | Russell J. Houghton, Claude L. Bertin, John A. Fifield, William R. Tonti | 1998-05-26 |
| 5686843 | Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module | Kenneth E. Beilstein, Jr., Claude L. Bertin, Dennis Charles Dubois, Wayne J. Howell, Gordon A. Kelley, Jr. +4 more | 1997-11-11 |
| 5644536 | High gain feedback latch | — | 1997-07-01 |
| 5640108 | Single stage dynamic receiver/decoder | — | 1997-06-17 |
| 5633605 | Dynamic bus with singular central precharge | Jeffrey S. Zimmerman, John A. Fifield, Robert E. Busch | 1997-05-27 |