Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6708298 | Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices | William E. Corbin, Jr., David P. Monty, Erik A. Nelson, Alan D. Norris, David Chapman +1 more | 2004-03-16 |
| 6658604 | Method for testing and guaranteeing that skew between two signals meets predetermined criteria | William R. J. Corbin, David P. Monty, Erik A. Nelson, Alan D. Norris, David Chapman +1 more | 2003-12-02 |
| 6438062 | Multiple memory bank command for synchronous DRAMs | Michael Curtis, William Paul Hovis | 2002-08-20 |
| 6434082 | Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock | William Paul Hovis | 2002-08-13 |
| 6289413 | Cached synchronous DRAM architecture having a mode register programmable cache policy | Jim L. Rogers, David Bondurant, Oscar Frederick Jones, Jr., Kenneth J. Mobley | 2001-09-11 |
| 6243283 | Impedance control using fuses | Claude L. Bertin, John A. Fifield, Erik L. Hedberg, Russell J. Houghton, Timothy D. Sullivan +1 more | 2001-06-05 |
| 6195027 | Capacitive precharging and discharging network for converting N bit input into M bit output | Claude L. Bertin, John A. Fifield, Russell J. Houghton, Christopher P. Miller, William R. Tonti | 2001-02-27 |
| 6178126 | Memory and system configuration for programming a redundancy address in an electric system | Toshiaki Kirihata, Paul W. Coteus, Warren E. Maule | 2001-01-23 |
| 6141245 | Impedance control using fuses | Claude L. Bertin, John A. Fifield, Erik L. Hedberg, Russell J. Houghton, Timothy D. Sullivan +1 more | 2000-10-31 |
| 5901093 | Redundancy architecture and method for block write access cycles permitting defective memory line replacement | Nathan R. Hiltebeitel, Robert Tamlyn, Thomas W. Wyckoff | 1999-05-04 |
| 5787457 | Cached synchronous DRAM architecture allowing concurrent DRAM operations | Christopher P. Miller, Jim L. Rogers | 1998-07-28 |
| 5745431 | Address transition detector (ATD) for power conservation | Dale E. Pontius, Toshiaki Kirihata, Robert Henry Kruggel | 1998-04-28 |
| 5430679 | Flexible redundancy architecture and fuse download scheme | Nathan R. Hiltebeitel, Dale E. Pontius | 1995-07-04 |
| 5065368 | Video RAM double buffer select control | Satish Chandra Gupta, Randall L. Henderson, Nathan R. Hiltebeitel, Robert Tamlyn, Todd Williams | 1991-11-12 |
| 5022006 | Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells | John A. Fifield | 1991-06-04 |
| 5001672 | Video ram with external select of active serial access register | Timothy J. Ebbers, Satish Chandra Gupta, Randall L. Henderson, Nathan R. Hiltebeitel, Robert Tamlyn +1 more | 1991-03-19 |
| 4984214 | Multiplexed serial register architecture for VRAM | Nathan R. Hiltebeitel, Robert Tamlyn | 1991-01-08 |