| 8854073 |
Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patterns |
David A. Grosch, Marc D. Knox, Brian C. Noble |
2014-10-07 |
| 8125840 |
Reference level generation with offset compensation for sense amplifier |
John E. Barth, Jr. |
2012-02-28 |
| 7237165 |
Method for testing embedded DRAM arrays |
Laura S. Chadwick, William R. J. Corbin, Jeffrey H. Dreibelbis, Thomas E. Obremski, Toshiharu Saitoh +1 more |
2007-06-26 |
| 7103814 |
Testing logic and embedded memory in parallel |
William R. J. Corbin, Brian R. Kessler, Thomas E. Obremski, Donald L. Wheater |
2006-09-05 |
| 7073100 |
Method for testing embedded DRAM arrays |
Laura S. Chadwick, William R. J. Corbin, Jeffrey H. Dreibelbis, Thomas E. Obremski, Toshiharu Saitoh +1 more |
2006-07-04 |
| 6856569 |
Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability |
Michael R. Ouellette |
2005-02-15 |
| 6708298 |
Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices |
William E. Corbin, Jr., David P. Monty, Alan D. Norris, Steven W. Tomashot, David Chapman +1 more |
2004-03-16 |
| 6658604 |
Method for testing and guaranteeing that skew between two signals meets predetermined criteria |
William R. J. Corbin, David P. Monty, Alan D. Norris, Steven W. Tomashot, David Chapman +1 more |
2003-12-02 |
| 6577548 |
Self timing interlock circuit for embedded DRAM |
John E. Barth, Jr., Jeffrey H. Dreibelbis |
2003-06-10 |
| 6449200 |
Duty-cycle-efficient SRAM cell test |
Harold Pilo |
2002-09-10 |
