Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7984329 | System and method for providing DRAM device-level repair via address remappings external to the device | Luis A. Lastras-Montano, Darren L. Anand, Charles A. Kilmer, Warren E. Maule, Robert B. Tremaine | 2011-07-19 |
| 7737766 | Two stage voltage boost circuit, IC and design structure | John A. Fifield | 2010-06-15 |
| 7733161 | Voltage boost system, IC and design structure | John A. Fifield | 2010-06-08 |
| 7710195 | Two stage voltage boost circuit with precharge circuit preventing leakage, IC and design structure | John A. Fifield | 2010-05-04 |
| 7472325 | Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable instructions and local higher-speed executable instructions | Kevin W. Gorman, Michael R. Nelms | 2008-12-30 |
| 7401281 | Remote BIST high speed test and redundancy calculation | Kevin W. Gorman, Michael R. Nelms | 2008-07-15 |
| 7237165 | Method for testing embedded DRAM arrays | Laura S. Chadwick, William R. J. Corbin, Erik A. Nelson, Thomas E. Obremski, Toshiharu Saitoh +1 more | 2007-06-26 |
| 7073100 | Method for testing embedded DRAM arrays | Laura S. Chadwick, William R. J. Corbin, Erik A. Nelson, Thomas E. Obremski, Toshiharu Saitoh +1 more | 2006-07-04 |
| 6766468 | Memory BIST and repair | John E. Barth, Jr., Michael R. Ouellette | 2004-07-20 |
| 6577548 | Self timing interlock circuit for embedded DRAM | John E. Barth, Jr., Erik A. Nelson | 2003-06-10 |
| 6507237 | Low-power DC voltage generator system | Louis L. Hsu, Rajiv V. Joshi, Russell J. Houghton, Wayne F. Ellis | 2003-01-14 |
| 6452848 | Programmable built-in self test (BIST) data generator for semiconductor memory devices | Thomas E. Obremski, Peter O. Jakobsen | 2002-09-17 |
| 6426904 | Structures for wafer level test and burn-in | John E. Barth, Jr., Claude L. Bertin, Wayne F. Ellis, Wayne J. Howell, Erik L. Hedberg +3 more | 2002-07-30 |
| 6337595 | Low-power DC voltage generator system | Louis L. Hsu, Rajiv V. Joshi, Russell J. Houghton, Wayne F. Ellis | 2002-01-08 |
| 6233184 | Structures for wafer level test and burn-in | John E. Barth, Jr., Claude L. Bertin, Wayne F. Ellis, Wayne J. Howell, Erik L. Hedberg +3 more | 2001-05-15 |
| 6185709 | Device for indicating the fixability of a logic circuit | Rex Kho, Leo A. Noel | 2001-02-06 |
| 6044024 | Interactive method for self-adjusted access on embedded DRAM memory macros | John E. Barth, Jr., Howard L. Kalter | 2000-03-28 |
| 5961653 | Processor based BIST for an embedded memory | Howard L. Kalter, John E. Barth, Jr., Rex Kho, John Stuart Parenteau, Jr., Donald L. Wheater +1 more | 1999-10-05 |
| 5875470 | Multi-port multiple-simultaneous-access DRAM chip | Wayne F. Ellis, Thomas J. Heller, Jr., Michael Ignatowski, Howard L. Kalter, David Meltzer | 1999-02-23 |
| 5682116 | Off chip driver having slew rate control and differential voltage protection circuitry | Thomas M. Maffitt | 1997-10-28 |
| 5463335 | Power up detection circuits | Sridhar Divakaruni, Wayne F. Ellis, Anatol Furman, Howard L. Kalter | 1995-10-31 |
| 5173906 | Built-in self test for integrated circuits | Erik L. Hedberg, John G. Petrovick, Jr. | 1992-12-22 |
| 5019772 | Test selection techniques | John A. Gabric, Erik L. Hedberg | 1991-05-28 |
| 4730122 | Power supply adapter systems | Roy C. Flaker, Erik L. Hedberg | 1988-03-08 |
| 4709162 | Off-chip driver circuits | George M. Braceras | 1987-11-24 |