Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11152063 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2021-10-19 |
| 10998045 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2021-05-04 |
| 10943658 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2021-03-09 |
| 10937496 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2021-03-02 |
| 10762959 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2020-09-01 |
| 10726897 | Trimming MRAM sense amp with offset cancellation | John K. DeBrosse, Matthew R. Wordeman | 2020-07-28 |
| 10726898 | MRAM sense amplifier with second stage offset cancellation | John Kenneth Debrose | 2020-07-28 |
| 10692576 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2020-06-23 |
| 10658022 | High gain sense amplifier with offset cancellation for magnetoresistive random access memory | — | 2020-05-19 |
| 10566057 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2020-02-18 |
| 10535403 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2020-01-14 |
| 10424375 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2019-09-24 |
| 10037802 | Phase change memory with an incrementally ramped write-reference voltage and an incrementally ramped read-reference voltage | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2018-07-31 |
| 9911492 | Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write period | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2018-03-06 |
| 9704575 | Content-addressable memory having multiple reference matchlines to reduce latency | Igor Arsovski, Michael T. Fragano, Robert M. Houle | 2017-07-11 |
| 9601200 | TCAM structures with reduced power supply noise | Igor Arsovski, Michael T. Fragano | 2017-03-21 |
| 9583192 | Matchline precharge architecture for self-reference matchline sensing | Igor Arsovski, Michael T. Fragano, Robert M. Houle | 2017-02-28 |
| 9502107 | Writing multiple levels in a phase change memory | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2016-11-22 |
| 9384792 | Offset-cancelling self-reference STT-MRAM sense amplifier | Anthony R. Bonaccio, John K. DeBrosse | 2016-07-05 |
| 9299431 | Writing multiple levels in a phase change memory using a write/read reference voltage ramping up over a write/read period | Chung H. Lam, Scott C. Lewis, Jack Morrish | 2016-03-29 |
| 8520458 | Phase change memory cycle timer and method | John A. Gabric, Mark C. H. Lamorey | 2013-08-27 |
| 8345475 | Non volatile cell and architecture with single bit random access read, program and erase | Chung H. Lam, Mark C. H. Lamorey | 2013-01-01 |
| 8300489 | Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump | John A. Fifield, Dale E. Pontius | 2012-10-30 |
| 8233345 | Phase change memory cycle timer and method | John A. Gabric, Mark C. H. Lamorey | 2012-07-31 |
| 7882455 | Circuit and method using distributed phase change elements for across-chip temperature profiling | Nazmul Habib, Mark C. H. Lamorey, Robert McMahon | 2011-02-01 |