RH

Robert M. Houle

IBM: 18 patents #6,125 of 70,183Top 9%
Globalfoundries: 4 patents #817 of 4,424Top 20%
GU Globalfoundries U.S.: 1 patents #22 of 211Top 15%
Overall (All Time): #173,530 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9916896 Ternary content addressable memory (TCAM) for multi bit miss detect circuit Igor Arsovski, Michael T. Fragano, Akhilesh Patil, Van Butler 2018-03-13
9890959 Universal tile installation mat for uncoupling floor or wall tiles set in mortar from a support surface Gregory Gelston, Guy J. Houle 2018-02-13
9859006 Algorithmic N search/M write ternary content addressable memory (TCAM) Igor Arsovski, Michael T. Fragano 2018-01-02
9704575 Content-addressable memory having multiple reference matchlines to reduce latency Igor Arsovski, Michael T. Fragano, Thomas M. Maffitt 2017-07-11
9583192 Matchline precharge architecture for self-reference matchline sensing Igor Arsovski, Michael T. Fragano, Thomas M. Maffitt 2017-02-28
9172371 Majority dominant power scheme for repeated structures and structures thereof Igor Arsovski 2015-10-27
8611169 Fine granularity power gating Steven H. Lamphier, Harold Pilo 2013-12-17
8582351 Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability Igor Arsovski, George M. Braceras, Kevin W. Gorman, Harold Pilo 2013-11-12
8525546 Majority dominant power scheme for repeated structures and structures thereof Igor Arsovski 2013-09-03
8233337 SRAM delay circuit that tracks bitcell characteristics Igor Arsovski, George M. Braceras, Harold Pilo 2012-07-31
8228713 SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same Igor Arsovski, John A. Fifield, Harold Pilo 2012-07-24
7986571 Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines Igor Arsovski, Michael T. Fragano 2011-07-26
7973549 Method and apparatus for calibrating internal pulses in an integrated circuit Rajiv V. Joshi, Robert L. Franch, Kevin A. Batson 2011-07-05
7944229 Method and apparatus for calibrating internal pulses in an integrated circuit Rajiv V. Joshi, Robert L. Franch, Kevin A. Batson 2011-05-17
7940581 Method for low power sensing in a multi-port SRAM using pre-discharged bit lines Igor Arsovski, Michael T. Fragano 2011-05-10
7869302 Programmable pulsewidth and delay generating circuit for integrated circuits Rajiv V. Joshi, Kevin A. Batson 2011-01-11
7859921 Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines Igor Arsovski, Michael T. Fragano 2010-12-28
7830727 Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines Igor Arsovski, Michael T. Fragano 2010-11-09
7701801 Programmable pulsewidth and delay generating circuit for integrated circuits Rajiv V. Joshi, Kevin A. Batson 2010-04-20
7042776 Method and circuit for dynamic read margin control of a memory array Miles G. Canada, Stephen F. Geissler, Dongho Lee, Vinod Ramadurai, Mathew I. Ringler +2 more 2006-05-09
5835504 Soft fuses using bist for cache self test David K. Balkin, Kenneth Torino, Sebastian T. Ventrone 1998-11-10
5691660 Clock synchronization scheme for fractional multiplication systems Robert E. Busch, KENNETH M. ZICK 1997-11-25
5668983 Precise stopping of a high speed microprocessor clock KENNETH M. ZICK 1997-09-16
5422835 Digital clock signal multiplier circuit Dac C. Pham 1995-06-06