Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7464217 | Design structure for content addressable memory | Geordie M. Braceras | 2008-12-09 |
| 7337268 | Content addressable memory structure | George M. Braceras | 2008-02-26 |
| 7120732 | Content addressable memory structure | George M. Braceras | 2006-10-10 |
| 7117400 | Memory device with data line steering and bitline redundancy | Kevin A. Batson, Garrett Stephen Koch, Fred J. Towler, Reid A. Wistort | 2006-10-03 |
| 6941435 | Integrated circuit having register configuration sets | Anthony R. Bonaccio, Barton E. Green, Frank Ray Keyser, III, Troy A. Seman | 2005-09-06 |
| 6791855 | Redundant array architecture for word replacement in CAM | Kevin A. Batson, Gary S. Koch, Fred J. Towler, Reid A. Wistort | 2004-09-14 |
| 6760240 | CAM cell with interdigitated search and bit lines | Albert M. Chu, Ezra D. B. Hall, Paul C. Parries, Daryl M. Seizter | 2004-07-06 |
| 6760881 | Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) | Kevin A. Batson, Albert M. Chu, Ezra D. B. Hall | 2004-07-06 |
| 6728123 | Redundant array architecture for word replacement in CAM | Kevin A. Batson, Gary S. Koch, Fred J. Towler, Reid A. Wistort | 2004-04-27 |
| 6687144 | High reliability content-addressable memory using shadow content-addressable memory | Kevin A. Batson, Geordie M. Braceras, Gary S. Koch | 2004-02-03 |
| 6650561 | High reliability content-addressable memory using shadow content-addressable memory | Kevin A. Batson, Geordie M. Braceras, Gary S. Koch | 2003-11-18 |
| 6501675 | Alternating reference wordline scheme for fast DRAM | Harold Pilo | 2002-12-31 |
| 6487101 | Use of search lines as global bitlines in a cam design | Jonathan B. Ashbrook, Albert M. Chu, Daryl M. Seitzer | 2002-11-26 |
| 6442055 | System and method for conserving power in a content addressable memory by providing an independent search line voltage | Kevin A. Batson | 2002-08-27 |
| 6430073 | Dram CAM cell with hidden refresh | Kevin A. Batson, Garrett Stephen Koch | 2002-08-06 |
| 6208572 | Semiconductor memory device having resistive bitline contact testing | R. Dean Adams, Harold Pilo, George E. Rudgers | 2001-03-27 |
| 6201750 | Scannable fuse latches | Fred J. Towler, Reid A. Wistort | 2001-03-13 |
| 5691660 | Clock synchronization scheme for fractional multiplication systems | KENNETH M. ZICK, Robert M. Houle | 1997-11-25 |
| 5633605 | Dynamic bus with singular central precharge | Jeffrey S. Zimmerman, John A. Fifield, Christopher P. Miller | 1997-05-27 |
| 5530836 | Method and apparatus for multiple memory bank selection | Endre P. Thoma | 1996-06-25 |
| 5276846 | Fast access memory structure | Frederick J. Aichelmann, Jr., Bruce E. Bachman, Theodore M. Redman, Endre P. Thoma | 1994-01-04 |
| 5036495 | Multiple mode-set for IC chip | William Paul Hovis, Theodore M. Redman, Endre P. Thoma, James A. Yankosky | 1991-07-30 |
| 4992984 | Memory module utilizing partially defective memory chips | Wayne F. Ellis, Theodore M. Redman, Endre P. Thoma | 1991-02-12 |
| 4807195 | Apparatus and method for providing a dual sense amplifier with divided bit line isolation | Endre P. Thoma | 1989-02-21 |