Issued Patents All Time
Showing 25 most recent of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332709 | Multi-element memory device with power for individual elements | Deborah Lindsey Dressler, Julia Kelly Cline | 2025-06-17 |
| 12094553 | Timing-drift calibration | Yohan U. Frans, Akash Bansal | 2024-09-17 |
| 11948619 | Protocol for memory power-mode control | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2024-04-02 |
| 11940857 | Multi-element memory device with power control for individual elements | Deborah Lindsey Dressler, Julia Kelly Cline | 2024-03-26 |
| 11908515 | 2T-1R architecture for resistive ram | Deepak C. Sekar, Brent Haukness, Gary B. Bronner, Thomas Vogelsang | 2024-02-20 |
| 11621030 | Protocol for memory power-mode control | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2023-04-04 |
| 11568929 | 2T-1R architecture for resistive RAM | Deepak C. Sekar, Brent Haukness, Gary B. Bronner, Thomas Vogelsang | 2023-01-31 |
| 11531386 | Multi-element memory device with power control for individual elements | Deborah Lindsey Dressler, Julia Kelly Cline | 2022-12-20 |
| 11250901 | Protocol for memory power-mode control | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2022-02-15 |
| 11211139 | Timing-drift calibration | Yohan U. Frans, Akash Bansal | 2021-12-28 |
| 11152062 | 1T-1R architecture for resistive random access memory | Deepak C. Sekar | 2021-10-19 |
| 11081176 | 2T-1R architecture for resistive RAM | Deepak C. Sekar, Brent Haukness, Gary B. Bronner, Thomas Vogelsang | 2021-08-03 |
| 10878878 | Protocol for memory power-mode control | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2020-12-29 |
| 10783964 | 1T-1R architecture for resistive random access memory | Deepak C. Sekar | 2020-09-22 |
| 10698464 | Multi-element memory device with power control for individual elements | Deborah Lindsey Dressler, Julia Kelly Cline | 2020-06-30 |
| 10672450 | Protocol for memory power-mode control | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2020-06-02 |
| 10650872 | Memory component with multiple command/address sampling modes | Frederick A. Ware, Ely Tsern, Brian S. Leibowitz, Akash Bansal, John Brooks +1 more | 2020-05-12 |
| 10622053 | Protocol for memory power-mode control | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2020-04-14 |
| 10622062 | 2T-1R architecture for resistive ram | Deepak C. Sekar, Brent Haukness, Gary B. Bronner, Thomas Vogelsang | 2020-04-14 |
| 10614869 | Protocol for memory power-mode control | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2020-04-07 |
| 10600497 | Timing-drift calibration | Yohan U. Frans, Akash Bansal | 2020-03-24 |
| 10388372 | 1T-1R architecture for resistive random access memory | Deepak C. Sekar | 2019-08-20 |
| 10262718 | DRAM having a plurality of registers | Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2019-04-16 |
| 10209922 | Communication via a memory interface | Liji Gopalakrishnan, Vlad Fruchter, Lawrence Lai, Pradeep Batra, Steven C. Woo | 2019-02-19 |
| 10199098 | 2T-1R architecture for resistive RAM | Deepak C. Sekar, Brent Haukness, Gary B. Bronner, Thomas Vogelsang | 2019-02-05 |