Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11948619 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2024-04-02 |
| 11621030 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2023-04-04 |
| 11250901 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2022-02-15 |
| 11194749 | Cross-threaded memory system | Frederick A. Ware | 2021-12-07 |
| 10878878 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2020-12-29 |
| 10672450 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2020-06-02 |
| 10650872 | Memory component with multiple command/address sampling modes | Frederick A. Ware, Ely Tsern, Brian S. Leibowitz, Wayne F. Ellis, Akash Bansal +1 more | 2020-05-12 |
| 10622053 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2020-04-14 |
| 10614869 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2020-04-07 |
| 10268619 | Cross-threaded memory system | Frederick A. Ware | 2019-04-23 |
| 10262718 | DRAM having a plurality of registers | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2019-04-16 |
| 10170170 | Memory control component with dynamic command/address signaling rate | Frederick A. Ware, Ely Tsern, Brian S. Leibowitz, Wayne F. Ellis, Akash Bansal +1 more | 2019-01-01 |
| 9886993 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2018-02-06 |
| 9818463 | Memory control component with inter-rank skew tolerance | Frederick A. Ware, Ely Tsern, Brian S. Leibowitz, Wayne F. Ellis, Akash Bansal +1 more | 2017-11-14 |
| 9563597 | High capacity memory systems with inter-rank skew tolerance | Frederick A. Ware, Ely Tsern, Brian S. Leibowitz, Wayne F. Ellis, Akash Bansal +1 more | 2017-02-07 |
| 9502096 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2016-11-22 |
| 9355021 | Cross-threaded memory system | Frederick A. Ware | 2016-05-31 |
| 9349422 | Supporting calibration for sub-rate operation in clocked memory systems | Akash Bansal, Yohan U. Frans, Todd Bystrom, Simon Li, Arun Vaidyanath | 2016-05-24 |
| 9111645 | Request-command encoding for reduced-data-rate testing | Wayne S. Richardson, Kurt Knorpp, Frederick A. Ware | 2015-08-18 |
| 9036436 | Supporting calibration for sub-rate operation in clocked memory systems | Akash Bansal, Yohan U. Frans, Todd Bystrom, Simon Li, Arun Vaidyanath | 2015-05-19 |
| 8942056 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai | 2015-01-27 |
| 8510495 | Cross-threaded memory system | Frederick A. Ware | 2013-08-13 |
| 8391099 | Integrated circuit memory device, system and method having interleaved row and column control | Lawrence Lai, Wayne S. Richardson | 2013-03-05 |
| 7940598 | Integrated circuit memory device, system and method having interleaved row and column control | Lawrence Lai, Wayne S. Richardson | 2011-05-10 |
| 7769942 | Cross-threaded memory system | Frederick A. Ware | 2010-08-03 |