Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393547 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2025-08-19 |
| 11973153 | Synchronous wired-or ACK status for memory with variable write latency | Yohan U. Frans, John Eric Linstadt, Jun Kim | 2024-04-30 |
| 11886375 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2024-01-30 |
| 11838153 | Digital signal processors providing scalable decision feedback equalization (DFE) employing sequence selection and related methods | Md Masum Hossain, Charles W. Boecker, Michael R. Trombley, Shaishav Desai | 2023-12-05 |
| 11341079 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2022-05-24 |
| 11184198 | Serial link receiver with improved bandwidth and accurate eye monitor | Marko Aleksic, Pravin Kumar Venkatesan, Nikhil Vaidya | 2021-11-23 |
| 11101393 | Synchronous wired-OR ACK status for memory with variable write latency | Yohan U. Frans, John Eric Linstadt, Jun Kim | 2021-08-24 |
| 10601615 | Serial link receiver with improved bandwidth and accurate eye monitor | Marko Aleksic, Pravin Kumar Venkatesan, Nikhil Vaidya | 2020-03-24 |
| 10468544 | Synchronous wired-OR ACK status for memory with variable write latency | Yohan U. Frans, Eric Linstadt, Jun Kim | 2019-11-05 |
| 10452601 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2019-10-22 |
| 10367636 | Phase calibration of clock signals | Marko Aleksic, Roxanne Vu | 2019-07-30 |
| 10135642 | Serial link receiver with improved bandwidth and accurate eye monitor | Marko Aleksic, Pravin Kumar Venkatesan, Nikhil Vaidya | 2018-11-20 |
| 10129015 | Phase calibration of clock signals | Marko Aleksic, Roxanne Vu | 2018-11-13 |
| 9940299 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2018-04-10 |
| 9755819 | Phase calibration of clock signals | Marko Aleksic, Roxanne Vu | 2017-09-05 |
| 9569396 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2017-02-14 |
| 9553380 | Card connector | Aihong Fang, Jianxin Wang, Mao Lu, Guoxiao Shen | 2017-01-24 |
| 9515204 | Synchronous wired-or ACK status for memory with variable write latency | Yohan U. Frans, Eric Lindstadt, Jun Kim | 2016-12-06 |
| 9349422 | Supporting calibration for sub-rate operation in clocked memory systems | Akash Bansal, Yohan U. Frans, Kishore Ven Kasamsetty, Todd Bystrom, Arun Vaidyanath | 2016-05-24 |
| 9330034 | Levelization of memory interface for communicating with multiple memory devices | Yohan U. Frans | 2016-05-03 |
| 9178647 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2015-11-03 |
| 9036436 | Supporting calibration for sub-rate operation in clocked memory systems | Akash Bansal, Yohan U. Frans, Kishore Ven Kasamsetty, Todd Bystrom, Arun Vaidyanath | 2015-05-19 |
| 8855217 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2014-10-07 |
| 8661615 | Pintle assembly | Philip Guo | 2014-03-04 |
| 8279948 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Nhat Nguyen | 2012-10-02 |