Issued Patents All Time
Showing 1–25 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393547 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2025-08-19 |
| 12316481 | Edge based partial response equalization | Brian S. Leibowitz, Jihong Ren, Ruwan Ratnayake | 2025-05-27 |
| 12316482 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2025-05-27 |
| 11886375 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2024-01-30 |
| 11793291 | Rotary type linear reciprocating motion device and applicator having the same | Chang Hwan HYUN, Kyung Won KIM, Eun Mi Kim | 2023-10-24 |
| 11539556 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2022-12-27 |
| 11525854 | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement | Jaeha Kim, Brian S. Leibowitz | 2022-12-13 |
| 11489703 | Edge based partial response equalization | Brian S. Leibowitz, Jihong Ren, Ruwan Ratnayake | 2022-11-01 |
| 11469927 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2022-10-11 |
| 11341079 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2022-05-24 |
| 11277254 | Receiver with enhanced clock and data recovery | Brian S. Leibowitz, Jaeha Kim, Jafar Savoj | 2022-03-15 |
| 11115247 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2021-09-07 |
| 11063741 | Phase control block for managing multiple clock domains in systems with frequency offsets | Jared L. Zerbe, Carl W. Werner | 2021-07-13 |
| 11063791 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Brian S. Leibowitz, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2021-07-13 |
| 11022639 | Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal | Jaeha Kim, Brian S. Leibowitz | 2021-06-01 |
| 10938605 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2021-03-02 |
| 10887076 | Receiver with enhanced clock and data recovery | Brian S. Leibowitz, Jaeha Kim, Jafar Savoj | 2021-01-05 |
| 10855496 | Edge based partial response equalization | Brian S. Leibowitz, Jihong Ren, Ruwan Ratnayake | 2020-12-01 |
| 10686632 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2020-06-16 |
| 10560291 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2020-02-11 |
| 10536304 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Brian S. Leibowitz, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2020-01-14 |
| 10466289 | Apparatus and method for controllably injecting jitter into recovered clock to simulate presence of jitter in input signal | Jaeha Kim, Brian S. Leibowitz | 2019-11-05 |
| 10454667 | Phase control block for managing multiple clock domains in systems with frequency offsets | Jared L. Zerbe, Carl W. Werner | 2019-10-22 |
| 10452601 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2019-10-22 |
| 10432389 | Receiver with enhanced clock and data recovery | Brian S. Leibowitz, Jaeha Kim, Jafar Savoj | 2019-10-01 |