Issued Patents All Time
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10135647 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2018-11-20 |
| 10135646 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2018-11-20 |
| 10044530 | Edge based partial response equalization | Brian S. Leibowitz, Jihong Ren, Ruwan Ratnayake | 2018-08-07 |
| 9973328 | Receiver with enhanced clock and data recovery | Brian S. Leibowitz, Jaeha Kim, Jafar Savoj | 2018-05-15 |
| 9940299 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2018-04-10 |
| 9912469 | Phase control block for managing multiple clock domains in systems with frequency offsets | Jared L. Zerbe, Carl W. Werner | 2018-03-06 |
| 9900189 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2018-02-20 |
| 9860089 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2018-01-02 |
| 9791492 | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement | Jaeha Kim, Brian Liebowitz | 2017-10-17 |
| 9774441 | Clock and data recovery using receiver clock spread spectrum modulation and offset compensation | Thomas Hastings Greer, III, Jade M. Kizer, Brian S. Leibowitz, Mark A. Horowitz | 2017-09-26 |
| 9748934 | Systems and methods for reducing power supply noise or jitter | Kyung Suk Oh, Yujeong Shim, Yanjing Ke, Tim Tri Hoang | 2017-08-29 |
| 9584306 | Phase detection in an analog clock data recovery circuit with decision feedback equalization | Wenyi Jin, Jihong Ren | 2017-02-28 |
| 9569396 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2017-02-14 |
| 9515814 | Phase control block for managing multiple clock domains in systems with frequency offsets | Jared L. Zerbe, Carl W. Werner | 2016-12-06 |
| 9455825 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Brian S. Leibowitz, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2016-09-27 |
| 9423441 | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement | Jaeha Kim, Brian S. Leibowitz | 2016-08-23 |
| 9425997 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2016-08-23 |
| 9419781 | Receiver with enhanced clock and data recovery | Brian S. Leibowitz, Jaeha Kim, Jafar Savoj | 2016-08-16 |
| 9419594 | Clock data recovery system | Andrew Joy, Arnold Feldman | 2016-08-16 |
| 9419663 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2016-08-16 |
| 9391816 | Edge based partial response equalization | Brian S. Leibowitz, Jihong Ren, Ruwan Ratnayake | 2016-07-12 |
| 9337992 | Clock and data recovery using receiver clock spread spectrum modulation and offset compensation | Thomas Hastings Greer, III, Jade M. Kizer, Brian S. Leibowitz, Mark A. Horowitz | 2016-05-10 |
| 9231601 | Techniques relating to phase-locked loop circuits | Kyung Suk Oh, Heetae Ahn | 2016-01-05 |
| 9178688 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Brian S. Leibowitz, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2015-11-03 |
| 9178647 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2015-11-03 |