Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9153572 | Integrated circuit system with dynamic decoupling and method of manufacture thereof | Kyung Suk Oh, Sergey Shumarayev, Boon Jin Ang, Guang Chen | 2015-10-06 |
| 9148156 | Phase detection circuits and methods | Farshid Aryanfar, Carl W. Werner | 2015-09-29 |
| 9106399 | Phase control block for managing multiple clock domains in systems with frequency offsets | Jared L. Zerbe, Carl W. Werner | 2015-08-11 |
| 9083280 | Techniques for phase detection | Brian S. Leibowitz, Farshid Aryanfar, Kun-Yung Chang, Jie Shen | 2015-07-14 |
| 9077575 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2015-07-07 |
| 9065453 | Signal distribution networks and related methods | Farshid Aryanfar, Kun-Yung Chang, Ting Wu, Carl W. Werner, Masoud Koochakzadeh | 2015-06-23 |
| 8934525 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Brian S. Leibowitz, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2015-01-13 |
| 8929496 | Receiver with enhanced clock and data recovery | Brian S. Leibowitz, Jaeha Kim, Jafar Savoj | 2015-01-06 |
| 8923467 | Clock and data recovery using receiver clock spread spectrum modulation and offset compensation | Thomas Hastings Greer, III, Jade M. Kizer, Brian S. Leibowitz, Mark A. Horowitz | 2014-12-30 |
| 8855217 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2014-10-07 |
| 8811553 | Edge based partial response equalization | Brian S. Leibowitz, Jihong Ren, Ruwan Ratnayake | 2014-08-19 |
| 8774337 | Phase control block for managing multiple clock domains in systems with frequency offsets | Jared L. Zerbe, Carl W. Werner | 2014-07-08 |
| 8619934 | Clock data recovery system | Arnold Feldman, Andrew Joy | 2013-12-31 |
| 8610474 | Signal distribution networks and related methods | Farshid Aryanfar, Kun-Yung Chang, Ting Wu, Carl W. Werner, Masoud Koochakzadeh | 2013-12-17 |
| 8548110 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Brian S. Leibowitz, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2013-10-01 |
| 8477835 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Jihong Ren, Qi Lin | 2013-07-02 |
| 8477834 | Partial response decision-feedback equalization with adaptation based on edge samples | Brian S. Leibowitz, Jihong Ren, Ruwan Ratnayake | 2013-07-02 |
| 8461882 | Driver supporting multiple signaling modes | Ken Kun-Yung Chang, Kashinath Prabhu | 2013-06-11 |
| 8422590 | Apparatus and methods for differential signal receiving | Brian S. Leibowitz, Jaeha Kim | 2013-04-16 |
| 8341450 | Continuous timing calibrated memory interface | Kun-Yung Chang, Fariborz Assaderaghi | 2012-12-25 |
| 8331512 | Phase control block for managing multiple clock domains in systems with frequency offsets | Jared L. Zerbe, Carl W. Werner | 2012-12-11 |
| 8311176 | Clock and data recovery employing piece-wise estimation on the derivative of the frequency | Thomas Hastings Greer, III, Jade M. Kizer, Brian S. Leibowitz, Mark A. Horowitz | 2012-11-13 |
| 8289032 | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement | Jaeha Kim, Brian S. Leibowitz | 2012-10-16 |
| 8279976 | Signaling with superimposed differential-mode and common-mode signals | Qi Lin, Jaeha Kim, Brian S. Leibowitz, Jared L. Zerbe, Jihong Ren | 2012-10-02 |
| 8279948 | Interface with variable data rate | Yohan U. Frans, Brian S. Leibowitz, Simon Li, Nhat Nguyen | 2012-10-02 |