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Methods and apparatus for performing clock and data duty cycle correction in a high-speed link |
Dinesh Patil, Tim Tri Hoang |
2021-09-07 |
| 10340904 |
Method and apparatus for phase-aligned 2X frequency clock generation |
— |
2019-07-02 |
| 9748934 |
Systems and methods for reducing power supply noise or jitter |
Kyung Suk Oh, Yujeong Shim, Tim Tri Hoang, Hae-Chang Lee |
2017-08-29 |
| 9231631 |
Circuits and methods for adjusting the voltage swing of a signal |
Tim Tri Hoang |
2016-01-05 |
| 9100112 |
Latency built-in self-test |
Han Hua Leong |
2015-08-04 |
| 9054721 |
Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter |
Wei Li, Weiqi Ding |
2015-06-09 |
| 8837571 |
Apparatus and methods for on-die instrumentation |
Thungoc M. Tran, Weiqi Ding, Jie Shen, Xiong Liu, Sangeeta Raman +1 more |
2014-09-16 |
| 8674862 |
Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter |
Wei Li, Weiqi Ding |
2014-03-18 |
| 8416001 |
Techniques for reducing duty cycle distortion in periodic signals |
Weiqi Ding, Sergey Shumarayev, Wilson Wong, Tim Tri Hoang |
2013-04-09 |
| 8395421 |
Configurable buffer circuits and methods |
Weiqi Ding, Sergey Shumarayev |
2013-03-12 |
| 8174294 |
Configurable buffer circuits and methods |
Weiqi Ding, Sergey Shumarayev |
2012-05-08 |
| 7861105 |
Clock data recovery (CDR) system using interpolator and timing loop module |
Jianbin Hao, Ning Zhu |
2010-12-28 |
| 7692497 |
PLLS covering wide operating frequency ranges |
Jianbin Hao, Ning Zhu |
2010-04-06 |