Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7308621 | Testing of ECC memories | Gerard M. Salem, Timothy J. von Reyn | 2007-12-11 |
| 7203873 | Asynchronous control of memory self test | Robert Abbott, Xiaoliang Bai, Dwayne Burek | 2007-04-10 |
| 7168005 | Programable multi-port memory BIST with compact microcode | Thomas J. Eckenrode, Steven Lee Gregor, Kamran Zarrineh | 2007-01-23 |
| 7149941 | Optimized ECC/redundancy fault recovery | Gerard M. Salem, Timothy J. von Reyn | 2006-12-12 |
| 7032144 | Method and apparatus for testing multi-port memories | Thomas J. Eckenrode, Steven Lee Gregor, Kamran Zarrineh | 2006-04-18 |
| 7003704 | Two-dimensional redundancy calculation | Thomas J. Eckenrode, Steven Lee Gregor, Garrett Stephen Koch | 2006-02-21 |
| 6907554 | Built-in self test system and method for two-dimensional memory redundancy allocation | Thomas J. Eckenrode, Steven Lee Gregor, Gary S. Koch | 2005-06-14 |
| 6874111 | System initialization of microcode-based memory built-in self-test | Thomas J. Eckenrode, Steven Lee Gregor, Kamran Zarrineh | 2005-03-29 |
| 6681350 | Method and apparatus for testing memory cells for data retention faults | Aneesha P. Deo, Kamran Zarrineh | 2004-01-20 |
| 6651201 | Programmable memory built-in self-test combining microcode and finite state machine self-test | Thomas J. Eckenrode, Steven Lee Gregor, Kamran Zarrineh | 2003-11-18 |
| 6557127 | Method and apparatus for testing multi-port memories | Thomas J. Eckenrode, Steven Lee Gregor, Kamran Zarrineh | 2003-04-29 |
| 6208572 | Semiconductor memory device having resistive bitline contact testing | Robert E. Busch, Harold Pilo, George E. Rudgers | 2001-03-27 |
| 6181155 | Method and apparatus for testing dynamic logic using an improved reset pulse | Patrick R. Hansen | 2001-01-30 |
| 6163862 | On-chip test circuit for evaluating an on-chip signal using an external test signal | Edmond S. Cooley, Patrick R. Hansen | 2000-12-19 |
| 5912901 | Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure | Michael R. Ouellette, Ronald J. Prilik | 1999-06-15 |
| 5592142 | High speed greater than or equal to compare circuit | Donald Albert Evans, Roy C. Flaker | 1997-01-07 |