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Aneesha P. Deo

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Endicott, NY: #387 of 620 inventorsTop 65%
🗺 New York: #67,335 of 115,490 inventorsTop 60%
Overall (All Time): #3,467,770 of 4,157,543Top 85%
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Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6681350 Method and apparatus for testing memory cells for data retention faults R. Dean Adams, Kamran Zarrineh 2004-01-20