Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11378623 | Diagnostic enhancement for multiple instances of identical structures | Steven M. Douskey, Orazio P. Forlenza, Mary P. Kusko, Franco Motika | 2022-07-05 |
| 10930364 | Iterative functional test exerciser reload and execution | Franco Motika, Mary P. Kusko | 2021-02-23 |
| 10613142 | Non-destructive recirculation test support for integrated circuits | Mary P. Kusko, Franco Motika | 2020-04-07 |
| 10598526 | Methods and systems for performing test and calibration of integrated sensors | Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Tobias Webel | 2020-03-24 |
| 10585142 | Functional diagnostics based on dynamic selection of alternate clocking | Mary P. Kusko, Franco Motika | 2020-03-10 |
| 10571519 | Performing system functional test on a chip having partial-good portions | Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker | 2020-02-25 |
| 10545188 | Functional diagnostics based on dynamic selection of alternate clocking | Mary P. Kusko, Franco Motika | 2020-01-28 |
| 10365132 | Methods and systems for performing test and calibration of integrated sensors | Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Tobias Webel | 2019-07-30 |
| 10247776 | Structurally assisted functional test and diagnostics for integrated circuits | Mary P. Kusko, Franco Motika | 2019-04-02 |
| 10209306 | Methods and systems for generating functional test patterns for manufacture test | Franco Motika, John D. Parker | 2019-02-19 |
| 10203371 | Methods and systems for generating functional test patterns for manufacture test | Franco Motika, John D. Parker | 2019-02-12 |
| 9857422 | Methods and systems for generating functional test patterns for manufacture test | Franco Motika, John D. Parker | 2018-01-02 |
| 9733307 | Optimized chain diagnostic fail isolation | Andrew A. Turner | 2017-08-15 |
| 8984335 | Core diagnostics and repair | Sreekala Anandavally, Anand Haridass, Diyanesh B.C. Vidyapoornachary | 2015-03-17 |
| 8977895 | Multi-core diagnostics and repair using firmware and spare cores | Sreekala Anandavally, Anand Haridass, Diyanesh B.C. Vidyapoornachary | 2015-03-10 |
| 8495287 | Clock-based debugging for embedded dynamic random access memory element in a processor core | Adam B. Collura, Michael Fee, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2013-07-23 |
| 8438431 | Support element office mode array repair code verification | Edward C. McCain, Lisa Nayak | 2013-05-07 |
| 8169321 | Radio frequency-enabled electromigration fuse | Subramanian S. Iyer, Chandrasekharan Kothandaraman | 2012-05-01 |
| 7308621 | Testing of ECC memories | R. Dean Adams, Timothy J. von Reyn | 2007-12-11 |
| 7194715 | Method and system for performing static timing analysis on digital electronic circuits | Steven E. Charlebois | 2007-03-20 |
| 7149941 | Optimized ECC/redundancy fault recovery | R. Dean Adams, Timothy J. von Reyn | 2006-12-12 |
| 7042776 | Method and circuit for dynamic read margin control of a memory array | Miles G. Canada, Stephen F. Geissler, Robert M. Houle, Dongho Lee, Vinod Ramadurai +2 more | 2006-05-09 |
| 6989696 | System and method for synchronizing divide-by counters | Rolf Hilgendorf, Jens Kuenzer, Cedric Lichtenau, Thomas Pflueger, Mathew I. Ringler +3 more | 2006-01-24 |
| 6643807 | Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test | Jay G. Heaslip, Gary W. Maier, Timothy J. von Reyn | 2003-11-04 |
| 5844917 | Method for testing adapter card ASIC using reconfigurable logic | Robert J. Lynch | 1998-12-01 |