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ATE compatible high-efficient functional test |
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Constrained pseudorandom test pattern for in-system logic built-in self-test |
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Electronic circuit having serial latch scan chains |
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2019-10-29 |
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Layout effect characterization for integrated circuits |
Martin Eckert, Thomas Gentner, Antje Mueller, Thomas Strach, Otto A. Torreiter |
2018-10-30 |
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Layout effect characterization for integrated circuits |
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2018-02-27 |
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Layout effect characterization for integrated circuits |
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2017-08-22 |
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Method, system, computer program product, and data processing device for monitoring memory circuits and corresponding integrated circuit |
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2013-01-29 |
| 7996738 |
Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip |
Tobias Gemmeke, Christoph Jaeschke, Cedric Lichtenau, Thomas Pflueger, Jochen Preiss |
2011-08-09 |
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Providing accurate time-based counters for scaling operating frequencies of microprocessors |
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2010-01-12 |
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Providing accurate time-based counters for scaling operating frequencies of microprocessors |
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System and method for synchronizing divide-by counters |
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2006-01-24 |
