Issued Patents All Time
Showing 25 most recent of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11262381 | Device for positioning a semiconductor die in a wafer prober | Otto A. Torreiter, Jörg Georg Appinger, Quintino L. Trianni | 2022-03-01 |
| 11239152 | Integrated circuit with optical tunnel | Otto A. Torreiter, Thomas Gentner | 2022-02-01 |
| 11209479 | Stressing integrated circuits using a radiation source | Matthias Pflanz, Otto A. Torreiter, Juergen Pille | 2021-12-28 |
| 10955440 | Probe card alignment | Roland Dieterle, Siegfried Tomaschko | 2021-03-23 |
| 10684930 | Functional testing of high-speed serial links | Thomas Gentner, Marta Junginger, Eckhard Kunigkeit, Matthias Pflanz, Quintino L. Trianni | 2020-06-16 |
| 10614884 | Content addressable memory with match hit quality indication | Alexander Fritsch | 2020-04-07 |
| 10605649 | Adjustable load transmitter | Siegfried Tomaschko, Roland Dieterle | 2020-03-31 |
| 10527649 | Probe card alignment | Roland Dieterle, Siegfried Tomaschko | 2020-01-07 |
| 10422817 | Probe card alignment | Roland Dieterle, Siegfried Tomaschko | 2019-09-24 |
| 10347337 | Content addressable memory with match hit quality indication | Alexander Fritsch | 2019-07-09 |
| 10345136 | Adjustable load transmitter | Siegfried Tomaschko, Roland Dieterle | 2019-07-09 |
| 10146144 | Adjustable load transmitter | Siegfried Tomaschko, Roland Dieterle | 2018-12-04 |
| 10114069 | Method for electrical testing of a 3-D chip stack | Eckhard Kunigkeit, Otto A. Torreiter, Quintino L. Trianni | 2018-10-30 |
| 10114914 | Layout effect characterization for integrated circuits | Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter | 2018-10-30 |
| 10082419 | Adjustable load transmitter | Siegfried Tomaschko, Roland Dieterle | 2018-09-25 |
| 10082526 | Probe card alignment | Roland Dieterle, Siegfried Tomaschko | 2018-09-25 |
| 10056346 | Chip attach frame | Otto A. Torreiter, Quintino L. Trianni | 2018-08-21 |
| 9977053 | Wafer probe alignment | Joerg G. Appinger, Eberhard Dengler, Roland Dieterle, Gabriele Kuczera, Siegfried Tomaschko +2 more | 2018-05-22 |
| 9927463 | Wafer probe alignment | Joerg G. Appinger, Eberhard Dengler, Roland Dieterle, Gabriele Kuczera, Siegfried Tomaschko +2 more | 2018-03-27 |
| 9904748 | Layout effect characterization for integrated circuits | Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter | 2018-02-27 |
| 9892789 | Content addressable memory with match hit quality indication | Alexander Fritsch | 2018-02-13 |
| 9891272 | Module testing utilizing wafer probe test equipment | Eckhard Kunigkeit, Quintino L. Trianni, Christian Zoellin | 2018-02-13 |
| 9885748 | Module testing utilizing wafer probe test equipment | Eckhard Kunigkeit, Quintino L. Trianni, Christian Zoellin | 2018-02-06 |
| 9804231 | Power noise histogram of a computer system | Hubert Harrer, Thomas Strach | 2017-10-31 |
| 9740813 | Layout effect characterization for integrated circuits | Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter | 2017-08-22 |