Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9477419 | Memory control system for a non-volatile memory and control method | Julien Penders, Carlos Agell | 2016-10-25 |
| 9425795 | Circuit and method for detection and compensation of transistor mismatch | Maryam Ashouei | 2016-08-23 |
| 8860502 | Method and apparatus for monitoring timing of critical paths | Mario Konijnenburg | 2014-10-14 |
| 8756263 | Binary logic unit and method to operate a binary logic unit | Jochen Preiss | 2014-06-17 |
| 8452824 | Binary logic unit and method to operate a binary logic unit | Jochen Preiss | 2013-05-28 |
| 8370409 | Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing | Nicolas Maeding, Jochen Preiss | 2013-02-05 |
| 8312069 | Permute unit and method to operate a permute unit | Jens Leenstra, Dieter Wendel | 2012-11-13 |
| 8266411 | Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance | Markus Kaltenbach, Nicolas Maeding | 2012-09-11 |
| 7996738 | Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip | Christoph Jaeschke, Jens Kuenzer, Cedric Lichtenau, Thomas Pflueger, Jochen Preiss | 2011-08-09 |
| 7962538 | Method of operand width reduction to enable usage of narrower saturation adder | Jens Leenstra, Nicolas Maeding, Kerstin Claudia Schelm | 2011-06-14 |
| 7913132 | System and method for scanning sequential logic elements | Dieter Wendel, Holger Wetter, Jens Leenstra | 2011-03-22 |
| 7890901 | Method and system for verifying the equivalence of digital circuits | Jens Leenstra, Nicolas Maeding, Hari Mony | 2011-02-15 |
| 7849428 | Formally deriving a minimal clock-gating scheme | Harry Barowski, J. Adam Butts, Nicolas Maeding, Viresh Paruthi | 2010-12-07 |
| 7795914 | Circuit design methodology to reduce leakage power | Friedrich Schroeder, Stefan Bonsels, Dieter Wendel | 2010-09-14 |
| 7735038 | Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit | Jens Leenstra, Jochen Preiss | 2010-06-08 |
| 7639046 | Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit | Jens Leenstra, Jochen Preiss | 2009-12-29 |
| 7624363 | Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes | Jason R. Baumgartner, Nicolas Maeding, Kai Weber | 2009-11-24 |
| 7509511 | Reducing register file leakage current within a processor | Harry Barowski, Jens Leenstra, Tim Niggemeier | 2009-03-24 |
| 7502918 | Method and system for data dependent performance increment and power reduction | Harry Barowski, Tim Niggemeier, Thomas Pflueger | 2009-03-10 |