Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12120222 | Deploying a system-specific secret in a highly resilient computer system | Reinhard T. Buendgen, Brian W. Stocker, Jonathan D. Bradbury | 2024-10-15 |
| 12095916 | Chained manifest for key management and attestation | Angel Nunez Mencias, Stefan Liesche | 2024-09-17 |
| 11824984 | Storage encryption for a trusted execution environment | Angel Nunez Mencias, Peter Morjan, Dirk Herrendoerfer, James Robert Magowan, Anbazhagan Mani | 2023-11-21 |
| 11755721 | Trusted workload execution | Angel Nunez Mencias, Peter Morjan, Dirk Herrendoerfer | 2023-09-12 |
| 11645092 | Building and deploying an application | Dirk Herrendoerfer, Peter Morjan, Angel Nunez Mencias | 2023-05-09 |
| 10317465 | Integrated circuit chip and a method for testing the same | Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Christian Zoellin | 2019-06-11 |
| 10006965 | Integrated circuit chip and a method for testing the same | Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Christian Zoellin | 2018-06-26 |
| 9506986 | Integrated circuit chip and a method for testing the same | Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Christian Zoellin | 2016-11-29 |
| 8370409 | Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing | Tobias Gemmeke, Jochen Preiss | 2013-02-05 |
| 8266411 | Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance | Tobias Gemmeke, Markus Kaltenbach | 2012-09-11 |
| 8145804 | Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor | Brian Flachs, Brad W. Michael, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi | 2012-03-27 |
| 8046566 | Method to reduce power consumption of a register file with multi SMT support | Christopher M. Abernathy, Jens Leenstra, Dung Q. Nguyen | 2011-10-25 |
| 7962538 | Method of operand width reduction to enable usage of narrower saturation adder | Tobias Gemmeke, Jens Leenstra, Kerstin Claudia Schelm | 2011-06-14 |
| 7890901 | Method and system for verifying the equivalence of digital circuits | Tobias Gemmeke, Jens Leenstra, Hari Mony | 2011-02-15 |
| 7849428 | Formally deriving a minimal clock-gating scheme | Harry Barowski, J. Adam Butts, Tobias Gemmeke, Viresh Paruthi | 2010-12-07 |
| 7783690 | Electronic circuit for implementing a permutation operation | Jens Leenstra, Amaury Neve de Mevergnies, Hans-Werner Tast | 2010-08-24 |
| 7769986 | Method and apparatus for register renaming | Christopher M. Abernathy, William E. Burky, Jens Leenstra | 2010-08-03 |
| 7676778 | Circuit design optimization of integrated circuit based clock gated memory elements | Eli Arbel, Cynthia Rae Eisner, Alexander Itskovich | 2010-03-09 |
| 7624363 | Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes | Jason R. Baumgartner, Tobias Gemmeke, Kai Weber | 2009-11-24 |