Issued Patents All Time
Showing 1–25 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204832 | Logical clock connection in an integrated circuit design | Ali S. El-Zein, Alvan W. Ng, Benedikt Geukes, Klaus-Dieter Schubert, Robert Alan Cargnoni +6 more | 2025-01-21 |
| 12050852 | Signal pre-routing in an integrated circuit design | Wolfgang Roesner, Ali S. El-Zein, Stephen G. Shuma, Stephen John Barnfield, Alvan W. Ng +1 more | 2024-07-30 |
| 11740872 | Detection of unintended dependencies in hardware designs with pseudo-random number generators | Bradley Donald Bingham, Jason R. Baumgartner, Praveen S. Reddy | 2023-08-29 |
| 11733295 | Methods and systems for identifying flaws and bugs in integrated circuits, for example, microprocessors | Arun Joseph, Wolfgang Roesner, Shiladitya Ghosh, Spandana V. Rachamalla | 2023-08-22 |
| 11675009 | Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors | Bradley Donald Bingham | 2023-06-13 |
| 11663381 | Clock mapping in an integrated circuit design | Stephen G. Shuma, Ali S. El-Zein, Wolfgang Roesner, Benedikt Geukes, Klaus-Dieter Schubert +3 more | 2023-05-30 |
| 11200361 | Scalable model checking in functional verification by integrating user-guided abstraction | Bradley Donald Bingham, Steven M. German | 2021-12-14 |
| 11150298 | Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors | Bradley Donald Bingham | 2021-10-19 |
| 10970444 | Methods and systems to verify correctness of bug fixes in integrated circuits | Bradley Donald Bingham, Abrar Polani | 2021-04-06 |
| 10565338 | Equivalency verification for hierarchical references | Ali S. El-Zein, Mark A. Williams, Robert L. Kanzelman, Wolfgang Roesner | 2020-02-18 |
| 9471327 | Verifying forwarding paths in pipelines | Anand B. Arunagiri, Udo Krautz, Sujeet Kumar | 2016-10-18 |
| 9459878 | Verifying forwarding paths in pipelines | Anand B. Arunagiri, Udo Krautz, Sujeet Kumar | 2016-10-04 |
| 9436582 | Calculating an immediate parent assertion statement for program verification | Mitra Purandare | 2016-09-06 |
| 9280496 | Formal verification of arbiters | Gadiel Auerbach, Fady Copty | 2016-03-08 |
| 9063807 | Method and structure for provably fair random number generator | Krishnan K. Kailas, Brian Chan Monwai | 2015-06-23 |
| 8799837 | Optimizing a netlist circuit representation by leveraging binary decision diagrams to perform rewriting | Jason R. Baumgartner, Geert Janssen, Robert L. Kanzelman | 2014-08-05 |
| 8756543 | Verifying data intensive state transition machines related application | Peter A. Sandon, Jun Sawada | 2014-06-17 |
| 8640065 | Circuit verification using computational algebraic geometry | Gradus Janssen, Luis A. Lastras-Montano, Alexey Y. Lvov, Robert J. Shadowen, Barry M. Trager +2 more | 2014-01-28 |
| 8473882 | Method and system for scalable reduction in registers with SAT-based resubstitution | Jason R. Baumgartner, Michael L. Case, Hari Mony | 2013-06-25 |
| 8397189 | Model checking in state transition machine verification | Peter A. Sandon, Jun Sawada | 2013-03-12 |
| 8370553 | Formal verification of random priority-based arbiters using property strengthening and underapproximations | Gadiel Auerbach, Fady Copty, David J. Levitt | 2013-02-05 |
| 8312071 | Method and structure for provably fair random number generator | Krishnan K. Kailas, Brian Chan Monwai | 2012-11-13 |
| 8201115 | Scalable reduction in registers with SAT-based resubstitution | Jason R. Baumgartner, Michael L. Case, Hari Mony | 2012-06-12 |
| 8185852 | Performing minimization of input count during structural netlist overapproximation | Jason R. Baumgartner, Robert L. Kanzelman, Hari Mony | 2012-05-22 |
| 8141048 | Sequential encoding for relational analysis (SERA) of a software model | Jason R. Baumgartner, Ali S. El-Zein, Fadi A. Zaraket | 2012-03-20 |