Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907361 | System and method for supporting secure objects using a memory access control monitor | Richard H. Boivie, Kattamuri Ekanadham, Kenneth A. Goldman, William E. Hall, Guerney D. H. Hunt +5 more | 2024-02-20 |
| 11165766 | Implementing authentication protocol for merging multiple server nodes with trusted platform modules utilizing provisioned node certificates to support concurrent node add and remove | Timothy R. Block, Elaine R. Palmer, Kenneth A. Goldman, William E. Hall, Hugo M. Krawczyk +3 more | 2021-11-02 |
| 10824952 | Reconfigurable array processor for pattern matching | Bulent Abali, Ganesh Balakrishnan, Bartholomew Blaner, Jeffrey A. Stuecheli | 2020-11-03 |
| 10824953 | Reconfigurable array processor for pattern matching | Bulent Abali, Ganesh Balakrishnan, Bartholomew Blaner, Jeffrey A. Stuecheli | 2020-11-03 |
| 10628579 | System and method for supporting secure objects using a memory access control monitor | Richard H. Boivie, Kattamuri Ekanadham, Kenneth A. Goldman, William E. Hall, Guerney Douglass Holloway Hunt +5 more | 2020-04-21 |
| 9779258 | Confidential extraction of system internal data | William E. Hall, Andreas C. Koenig, Cedric Lichtenau, Elaine R. Palmer, Thomas Pflueger | 2017-10-03 |
| 9189380 | Systems and methods to save and restore a write gather pipe | Milan Shah | 2015-11-17 |
| 8988139 | Self-selected variable power integrated circuit | Nghia V. Phan, Jonathan H. Raymond | 2015-03-24 |
| 8756543 | Verifying data intensive state transition machines related application | Viresh Paruthi, Jun Sawada | 2014-06-17 |
| 8397189 | Model checking in state transition machine verification | Viresh Paruthi, Jun Sawada | 2013-03-12 |
| 8347019 | Structure for hardware assisted bus state transition circuit using content addressable memories | Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Jason M. Norman +2 more | 2013-01-01 |
| 8291357 | On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations | Serafino Bueti, Adam J. Courchesne, Kenneth J. Goodnow, Todd E. Leonard, Peter A. Twombly +1 more | 2012-10-16 |
| 8146046 | Structures for semiconductor structures with error detection and correction | Timothy J. Dalton, Marc R. Faucher, Paul D. Kartschoke | 2012-03-27 |
| 8132136 | Dynamic critical path detector for digital logic circuit paths | Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Peter A. Twombly +1 more | 2012-03-06 |
| 8108609 | Structure for implementing dynamic refresh protocols for DRAM based cache | John E. Barth, Jr., Philip G. Emma, Erik L. Hedberg, Hillery C. Hunter, Vijayalakshmi Srinivasan +1 more | 2012-01-31 |
| 8108753 | Method of computing partial CRCs | Richard E. Anderson, Christos J. Georgiou | 2012-01-31 |
| 8024513 | Method and system for implementing dynamic refresh protocols for DRAM based cache | John E. Barth, Jr., Philip G. Emma, Erik L. Hedberg, Hillery C. Hunter, Vijayalakshmi Srinivasan +1 more | 2011-09-20 |
| 8019970 | Three-dimensional networking design structure | Kerry Bernstein, Timothy J. Dalton, Marc R. Faucher | 2011-09-13 |
| 7971122 | Method of computing partial CRCS | Richard E. Anderson, Christos J. Georgiou | 2011-06-28 |
| 7962695 | Method and system for integrating SRAM and DRAM architecture in set associative cache | Marc R. Faucher, Hillery C. Hunter, William Robert Reohr, Vijayalakshmi Srinivasan, Arnold S. Tran | 2011-06-14 |
| 7949853 | Two dimensional addressing of a matrix-vector register array | R. Michael P. West | 2011-05-24 |
| 7941772 | Dynamic critical path detector for digital logic circuit paths | Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Peter A. Twombly +1 more | 2011-05-10 |
| 7908460 | Method and apparatus for obtaining a scalar value directly from a vector register | Yu-Chung C. Liao, Howard Cheng, Timothy J. Van Hook | 2011-03-15 |
| 7882302 | Method and system for implementing prioritized refresh of DRAM based cache | Marc R. Faucher, Arnold S. Tran | 2011-02-01 |
| 7865749 | Method and apparatus for dynamic system-level frequency scaling | Cedric Lichtenau, Martin Recktenwald, Thomas Pflueger, Rolf Hilgendorf | 2011-01-04 |