GB

Ganesh Balakrishnan

IBM: 28 patents #3,676 of 70,183Top 6%
AM AMD: 23 patents #450 of 9,279Top 5%
ST Stc.Unm: 6 patents #50 of 604Top 9%
CS Core Scientific: 5 patents #8 of 26Top 35%
LP Lenovo (Singapore) Pte.: 4 patents #155 of 1,012Top 20%
CO Core Scientific Operating: 3 patents #1 of 16Top 7%
Motorola: 1 patents #6,475 of 12,470Top 55%
Microsoft: 1 patents #24,826 of 40,388Top 65%
Overall (All Time): #26,621 of 4,157,543Top 1%
73
Patents All Time

Issued Patents All Time

Showing 25 most recent of 73 patents

Patent #TitleCo-InventorsDate
12423241 Shadow tag management for accelerator partitions Amit P. Apte, Bryan P. Broussard, Vydhyanathan Kalyanasundharam 2025-09-23
12417179 Adaptive system probe action to minimize input/output dirty data transfers Li Ou, Amit P. Apte 2025-09-16
12399839 Dynamically controlled cache rinsing Chintan S. Patel, Alexander J. Branover, Joe Sargunaraj, Christopher J. Brennan, Akshay Lahiry +1 more 2025-08-26
12393532 Coherent block read fulfillment Vydhyanathan Kalyanasundharam, Amit P. Apte, Eric Christopher Morton, Ann Ling 2025-08-19
12189535 Tiered memory caching Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte 2025-01-07
12158845 Region based split-directory scheme to adapt to large cache sizes Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte 2024-12-03
12141066 Probe filter directory management Amit P. Apte, Kevin M. Lepak, Vydhyanathan Kalyanasundharam 2024-11-12
12112208 Switching of workloads according to switchover cost Kristy-Leigh Anne Minehan, Evan Adams, Carla Cortez, Ian Ferreira 2024-10-08
11954033 Page rinsing scheme to keep a directory page in an exclusive state in a single complex Amit P. Apte, Ann Ling, Vydhyanathan Kalyanasundharam 2024-04-09
11874783 Coherent block read fulfillment Vydhyanathan Kalyanasundharam, Amit P. Apte, Eric Christopher Morton, Ann Ling 2024-01-16
11874774 Mechanism to efficiently rinse memory-side cache of dirty data Ravindra N. Bhargava, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam 2024-01-16
11809322 Region based directory scheme to adapt to large cache sizes Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Eric Christopher Morton, Elizabeth M. Cooper +1 more 2023-11-07
11803470 Multi-level cache coherency protocol for cache line evictions Amit P. Apte, Ann Ling, Vydhyanathan Kalyanasundharam 2023-10-31
11782848 Home agent based cache transfer acceleration scheme Amit P. Apte, Vydhyanathan Kalyanasundharam, Kevin M. Lepak 2023-10-10
11748674 System and method for health reporting in a data center Carla Cortez, Aaron Strachan 2023-09-05
11669901 Communication network for gaming rewards 2023-06-06
11567821 Health reporting for computing devices Kristy-Leigh Anne Minehan, Evan Adams, Carla Cortez, Ian Ferreira 2023-01-31
11507517 Scalable region-based directory Amit P. Apte 2022-11-22
11489736 System and method for managing computing devices Kristy-Leigh Anne Minehan, Evan Adams, Gabrielle Gordon 2022-11-01
11314646 Region based split-directory scheme to adapt to large cache sizes Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte 2022-04-26
11249835 Automatic repair of computing devices in a data center Ian Ferreira, Evan Adams, Carla Cortez, Eric Hullander 2022-02-15
11178021 System and method for visually managing computing devices in a data center Thomas Fuller, Chandra Ponneganti, Kristy-Leigh Anne Minehan 2021-11-16
11119926 Region based directory scheme to adapt to large cache sizes Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Eric Christopher Morton, Elizabeth M. Cooper +1 more 2021-09-14
10922237 Accelerating accesses to private regions in a region-based cache directory scheme Vydhyanathan Kalyanasundharam, Amit P. Apte 2021-02-16
10824585 Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements Bartholomew Blaner, John J. Reilly, Jeffrey A. Stuecheli 2020-11-03