| 12282439 |
Dynamic page state aware scheduling of read/write burst transactions |
Guanhao Shen, Kedarnath Balakrishnan |
2025-04-22 |
| 12253961 |
Staging memory access requests |
James R. Magro, Kedarnath Balakrishnan, Guanhao Shen |
2025-03-18 |
| 11995008 |
Memory controller with hybrid DRAM/persistent memory channel arbitration |
Guanhao Shen, James R. Magro, Kedarnath Balakrishnan |
2024-05-28 |
| 11874774 |
Mechanism to efficiently rinse memory-side cache of dirty data |
Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam |
2024-01-16 |
| 11809322 |
Region based directory scheme to adapt to large cache sizes |
Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton +1 more |
2023-11-07 |
| 11789655 |
Efficient and low latency memory access scheduling |
Guanhao Shen |
2023-10-17 |
| 11782640 |
Efficient and low latency memory access scheduling |
Guanhao Shen |
2023-10-10 |
| 11755246 |
Efficient rank switching in multi-rank memory controller |
Guanhao Shen |
2023-09-12 |
| 11687281 |
DRAM command streak efficiency management |
Guanhao Shen |
2023-06-27 |
| 11625352 |
DRAM command streak management |
Guanhao Shen, Raghava Sravan Adidamu |
2023-04-11 |
| 11526278 |
Adaptive page close prediction |
Guanhao Shen, James R. Magro, Kedarnath Balakrishnan, Kevin M. Brandl |
2022-12-13 |
| 11429281 |
Speculative hint-triggered activation of pages in memory |
Philip Park, Vydhyanathan Kalyanasundharam, James R. Magro |
2022-08-30 |
| 11119926 |
Region based directory scheme to adapt to large cache sizes |
Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton +1 more |
2021-09-14 |
| 10846253 |
Dynamic page state aware scheduling of read/write burst transactions |
Guanhao Shen, Kedarnath Balakrishnan |
2020-11-24 |
| 10613764 |
Speculative hint-triggered activation of pages in memory |
Philip Park, Vydhyanathan Kalyanasundharam, James R. Magro |
2020-04-07 |
| 10572389 |
Cache control aware memory controller |
Ganesh Balakrishnan |
2020-02-25 |
| 10545875 |
Tag accelerator for low latency DRAM cache |
Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Ganesh Balakrishnan |
2020-01-28 |
| 10503648 |
Cache to cache data transfer acceleration techniques |
Vydhyanathan Kalyanasundharam, Amit P. Apte, Ganesh Balakrishnan, Ann Ling |
2019-12-10 |
| 10503670 |
Dynamic per-bank and all-bank refresh |
Guanhao Shen, James R. Magro, Kedarnath Balakrishnan, Jing Wang |
2019-12-10 |
| 10223124 |
Thread selection at a processor based on branch prediction confidence |
Ramkumar Jayaseelan |
2019-03-05 |
| 9529720 |
Variable distance bypass between tag array and data array pipelines in a cache |
Marius Evers, John Kalamatianos, Carl Dietz, Richard E. Klass |
2016-12-27 |
| 8909866 |
Prefetching to a cache based on buffer fullness |
John Kalamatianos, Ramkumar Jayaseelan |
2014-12-09 |
| 8782384 |
Branch history with polymorphic indirect branch information |
David N. Suggs |
2014-07-15 |
| 8667257 |
Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit |
David N. Suggs, Anthony Jarvis |
2014-03-04 |