Issued Patents All Time
Showing 25 most recent of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430136 | Systems and methods for branch misprediction aware cache prefetcher training | Jagadish B. Kotra, Gabriel H. Loh | 2025-09-30 |
| 12373207 | Implementing a micro-operation cache with compaction | Jagadish B. Kotra | 2025-07-29 |
| 12360907 | Region pattern-matching hardware prefetcher | Gabriel H. Loh, Marko Scrbak, Akhil Arunkumar | 2025-07-15 |
| 12339783 | Managing a cache using per memory region reuse distance estimation | Jagadish B. Kotra, Asmita Pal | 2025-06-24 |
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | Jagadish B. Kotra, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan, Patrick J. Shyvers +1 more | 2025-05-20 |
| 12287739 | Accessing a cache based on an address translation buffer result | Jagadish B. Kotra | 2025-04-29 |
| 12189953 | Speculative dram request enabling and disabling | Jagadish B. Kotra | 2025-01-07 |
| 12175073 | Reusing remote registers in processing in memory | Varun Agrawal, Niti Madan | 2024-12-24 |
| 12153926 | Processor-guided execution of offloaded instructions using fixed function operations | Michael T. Clark, Marius Evers, William L. Walker, Paul James Moyer, Jay Fleischman +1 more | 2024-11-26 |
| 12153524 | Apparatus, system, and method for throttling prefetchers to prevent training on irregular memory accesses | Marko Scrbak, Gabriel H. Loh, Akhil Arunkumar | 2024-11-26 |
| 12135653 | Flexible dictionary sharing for compressed caches | Alexander D. Breslow | 2024-11-05 |
| 12111767 | Method and apparatus for a page-local delta-based prefetcher | Susumu Mashimo | 2024-10-08 |
| 12105957 | Accelerating relaxed remote atomics on multiple writer operations | Karthik Ramu Sangaiah, Anthony Gutierrez | 2024-10-01 |
| 12073251 | Offloading computations from a processor to remote execution logic | Nagadastagiri Reddy Challapalle, Jagadish B. Kotra | 2024-08-27 |
| 12066950 | Approach for managing near-memory processing commands and non-near-memory processing commands in a memory controller | Niti Madan | 2024-08-20 |
| 12045169 | Hardware configuration selection using machine learning model | Furkan Eris, Paul Keltcher, Mayank Chhablani, Alok Garg | 2024-07-23 |
| 12026401 | DRAM row management for processing in memory | Niti Madan, Yasuko Eckert, Varun Agrawal | 2024-07-02 |
| 12019547 | Dispatch bandwidth of memory-centric requests by bypassing storage array address checking | Jagadish B. Kotra, Gagandeep Panwar | 2024-06-25 |
| 11960404 | Method and apparatus for reducing the latency of long latency memory requests | Jagadish B. Kotra | 2024-04-16 |
| 11921634 | Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host | Jagadish B. Kotra, Yasuko Eckert, Yonghae Kim | 2024-03-05 |
| 11874739 | Error detection and correction in memory modules using programmable ECC engines | Sudhanva Gurumurthi, Vilas Sridharan, Shaizeen Aga, Nuwan Jayasena, Michael Ignatowski +1 more | 2024-01-16 |
| 11868777 | Processor-guided execution of offloaded instructions using fixed function operations | Michael T. Clark, Marius Evers, William L. Walker, Paul James Moyer, Jay Fleischman +1 more | 2024-01-09 |
| 11847062 | Re-fetching data for L3 cache data evictions into a last-level cache | Tarun Nakra, Jay Fleischman, Gautam Tarasingh Hazari, Akhil Arunkumar, William L. Walker +2 more | 2023-12-19 |
| 11847061 | Approach for supporting memory-centric operations on cached data | Shaizeen Aga, Nuwan Jayasena | 2023-12-19 |
| 11842199 | Controlling the operating speed of stages of an asynchronous pipeline | Greg Sadowski, Shomit N. Das | 2023-12-12 |