| 12455823 |
Super-temporal cache replacement policy |
Gabriel H. Loh, Joseph L. Greathouse, Paul James Moyer |
2025-10-28 |
|
| 12430257 |
Smart cache cleaner |
Dilip Kumar Jha, Durgesh Kumar |
2025-09-30 |
|
| 12367145 |
Remote acceleration for data dependent address calculation |
Scott Thomas Bingham, Pongstorn Maidee, William E. Jones, Richard L. Carlson |
2025-07-22 |
|
| 12306754 |
Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches |
Jagadish B. Kotra, John Kalamatianos, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan +1 more |
2025-05-20 |
|
| 12153926 |
Processor-guided execution of offloaded instructions using fixed function operations |
John Kalamatianos, Michael T. Clark, Marius Evers, Paul James Moyer, Jay Fleischman +1 more |
2024-11-26 |
$172,029,000 |
| 11868777 |
Processor-guided execution of offloaded instructions using fixed function operations |
John Kalamatianos, Michael T. Clark, Marius Evers, Paul James Moyer, Jay Fleischman +1 more |
2024-01-09 |
$241,234,000 |
| 11847062 |
Re-fetching data for L3 cache data evictions into a last-level cache |
Tarun Nakra, Jay Fleischman, Gautam Tarasingh Hazari, Akhil Arunkumar, Gabriel H. Loh +2 more |
2023-12-19 |
$321,032,000 |
| 11829196 |
Ring transport employing clock wake suppression |
— |
2023-11-28 |
$314,875,000 |
| 11704248 |
Retaining cache entries of a processor core during a powered-down state |
Michael L. Golden, Marius Evers |
2023-07-18 |
$179,194,000 |
| 11675703 |
Memory request throttling to constrain memory bandwidth utilization |
William E. Jones |
2023-06-13 |
$166,732,000 |
| 11561906 |
Rinsing cache lines from a common memory page to memory |
William E. Jones |
2023-01-24 |
$206,859,000 |
| 11294810 |
Memory request throttling to constrain memory bandwidth utilization |
William E. Jones |
2022-04-05 |
$280,939,000 |
| 11226900 |
Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory |
Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, Michael W. Boyer |
2022-01-18 |
$263,340,000 |
| 11210246 |
Probe interrupt delivery |
Vydhyanathan Kalyanasundharam, Eric Christopher Morton, Bryan P. Broussard, Paul James Moyer |
2021-12-28 |
$188,037,000 |
| 10956332 |
Retaining cache entries of a processor core during a powered-down state |
Michael L. Golden, Marius Evers |
2021-03-23 |
$85,424,000 |
| 10740029 |
Expandable buffer for memory transactions |
Gabriel H. Loh |
2020-08-11 |
$73,029,000 |
| 10705958 |
Coherency directory entry allocation based on eviction costs |
Michael W. Boyer, Gabriel H. Loh, Yasuko Eckert |
2020-07-07 |
$35,622,000 |
| 10366027 |
I/O writes with cache steering |
Eric Christopher Morton, Elizabeth M. Cooper, Douglas Benson Hunt, Richard Martin Born, Richard H. Lee +3 more |
2019-07-30 |
$35,149,000 |
| 10289567 |
Systems and method for delayed cache utilization |
— |
2019-05-14 |
$20,760,000 |
| 10282295 |
Reducing cache footprint in cache coherence directory |
Michael W. Boyer, Yasuko Eckert, Gabriel H. Loh |
2019-05-07 |
$22,156,000 |
| 10073776 |
Shadow tag memory to monitor state of cachelines at different cache level |
Sriram Srinivasan |
2018-09-11 |
$37,012,000 |
| 9946646 |
Systems and method for delayed cache utilization |
— |
2018-04-17 |
$7,065,000 |
| 9940247 |
Concurrent access to cache dirty bits |
— |
2018-04-10 |
$10,802,000 |
| 9916243 |
Method and apparatus for performing a bus lock and translation lookaside buffer invalidation |
Paul James Moyer, Richard Martin Born, Eric Christopher Morton, David S. Christie, Marius Evers +1 more |
2018-03-13 |
$10,106,000 |
| 9864681 |
Dynamic multithreaded cache allocation |
— |
2018-01-09 |
$8,421,000 |
