| 12153926 |
Processor-guided execution of offloaded instructions using fixed function operations |
John Kalamatianos, Marius Evers, William L. Walker, Paul James Moyer, Jay Fleischman +1 more |
2024-11-26 |
$172,029,000 |
| 11868777 |
Processor-guided execution of offloaded instructions using fixed function operations |
John Kalamatianos, Marius Evers, William L. Walker, Paul James Moyer, Jay Fleischman +1 more |
2024-01-09 |
$241,234,000 |
| 11347289 |
Enabling performance features for voltage limited processors |
Mahesh Subramony, David N. Suggs, Matthew M. Crum |
2022-05-31 |
$369,633,000 |
| 11106596 |
Configurable skewed associativity in a translation lookaside buffer |
John M. King |
2021-08-31 |
$371,128,000 |
| 11061753 |
Platform first error handling |
Dean A. Liberty, Vilas Sridharan, Jelena Ilic, David S. Christie, James R. Williamson +1 more |
2021-07-13 |
$177,056,000 |
| 10223162 |
Mechanism for resource utilization metering in a computer system |
Jay Fleischman, Thaddeus Fortenberry, Maurice B. Steinman |
2019-03-05 |
$23,702,000 |
| 10214049 |
Spinner for vehicle wheel |
— |
2019-02-26 |
|
| 9527342 |
Spinner for vehicle wheel |
— |
2016-12-27 |
|
| 9110802 |
Processor and method implemented by a processor to implement mask load and store instructions |
Kelvin D. Goveas, Edward J. McLellan, Steven Beigelmacher, David E. Kroesche |
2015-08-18 |
$1,947,000 |
| 8882205 |
Spinner for vehicle wheel |
— |
2014-11-11 |
|
| 8145876 |
Address translation with multiple translation look aside buffers |
Michael E. Tuuk |
2012-03-27 |
$11,097,000 |
| 7937574 |
Precise counter hardware for microcode loops |
Jelena Ilic, Syed Faisal Ahmed, Michael Thomas Dibrino |
2011-05-03 |
$12,826,000 |
| 7831816 |
Non-destructive sideband reading of processor state information |
Wallace Paul Montgomery, David F. Tobias |
2010-11-09 |
$4,649,000 |
| 7761672 |
Data movement and initialization aggregation |
Matthew A. Rafacz |
2010-07-20 |
$12,141,000 |
| 7665002 |
Multi-core integrated circuit with shared debug port |
Scott White, Timothy J. Wood |
2010-02-16 |
$19,031,000 |
| 7565513 |
Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations |
Ashraf Ahmed, Kelvin D. Goveas, Jelena Ilic |
2009-07-21 |
$9,005,000 |
| 7490254 |
Increasing workload performance of one or more cores on multiple core processors |
— |
2009-02-10 |
$24,390,000 |
| 7373484 |
Controlling writes to non-renamed register space in an out-of-order execution microprocessor |
Arun Radhakrishnan, Benjamin T. Sander, Michael Filippo, David E. Kroesche |
2008-05-13 |
$15,194,000 |
| 7257679 |
Sharing monitored cache lines across multiple cores |
— |
2007-08-14 |
$3,919,000 |
| 7124286 |
Establishing an operating mode in a processor |
Kevin J. McGrath, James B. Keller |
2006-10-17 |
$21,769,000 |
| 6973562 |
Establishing an operating mode in a processor |
Kevin J. McGrath |
2005-12-06 |
$7,747,000 |
| 6968444 |
Microprocessor employing a fixed position dispatch unit |
David E. Kroesche |
2005-11-22 |
$6,256,000 |
| 6934903 |
Using microcode to correct ECC errors in a processor |
Chetana N. Keltcher, William A. Hughes, Bruce R. Holloway |
2005-08-23 |
$8,041,000 |
| 6898697 |
Efficient method for mode change detection and synchronization |
Hongwen Gao, Chetana N. Keltcher |
2005-05-24 |
$6,015,000 |
| 6625726 |
Method and apparatus for fault handling in computer systems |
Scott White |
2003-09-23 |
$3,430,000 |
