Issued Patents All Time
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12346187 | Systems and methods for clock gating | Arjun Pal Chowdury, Paul Walmsley | 2025-07-01 |
| 12086004 | Selectable and hierarchical power management | — | 2024-09-10 |
| 11880260 | Instruction subset implementation for low power operation | Elliot H. Mednick | 2024-01-23 |
| 11645209 | Method of cache prefetching that increases the hit rate of a next faster cache | Shay Gal-On, Srilatha Manne, Alexander Rucker | 2023-05-09 |
| 11080195 | Method of cache prefetching that increases the hit rate of a next faster cache | Shay Gal-On, Srilatha Manne, Alexander Rucker | 2021-08-03 |
| 10776119 | Combined conditional branch and indirect branch target predictor | David A. Carlson, Rohit P. Thakar | 2020-09-15 |
| 10747541 | Managing predictor selection for branch prediction | Shubhendu Sekhar Mukherjee, David William Kravitz | 2020-08-18 |
| 10698472 | Instruction subset implementation for low power operation | Elliot H. Mednick | 2020-06-30 |
| 10540181 | Managing branch prediction information for different contexts | Shubhendu Sekhar Mukherjee, Richard E. Kessler, David William Kravitz, Rabin Sugumar | 2020-01-21 |
| 10142258 | Methods and apparatus for processing in a network on chip (NOC) | Greg Sadowski | 2018-11-27 |
| 9575553 | Replica path timing adjustment and normalization for adaptive voltage and frequency scaling | Seng Oon Toh, Stephen V. Kosonocky, Michael L. Golden, Samuel D. Naffziger | 2017-02-21 |
| 9110802 | Processor and method implemented by a processor to implement mask load and store instructions | Kelvin D. Goveas, Steven Beigelmacher, David E. Kroesche, Michael T. Clark | 2015-08-18 |
| 9021207 | Management of cache size | John Kalamatianos, Paul Keltcher, Srilatha Manne, Richard E. Klass, James M. O'Connor | 2015-04-28 |
| 7647472 | High speed and high throughput digital communications processor with efficient cooperation between programmable processing components | Thomas B. Brightman, Andrew D. Funk, David J. Husak, Andrew Brown, John F. Brown +4 more | 2010-01-12 |
| 7100020 | Digital communications processor | Thomas B. Brightman, Andrew Brown, John F. Brown, James Arthur Farrell, Andrew D. Funk +4 more | 2006-08-29 |
| 6463523 | Method and apparatus for delaying the execution of dependent loads | Richard E. Kessler, Rahul Razdan | 2002-10-08 |
| 6449713 | Implementation of a conditional move instruction in an out-of-order processor | Joel S. Emer, Bruce E. Edwards, Daniel Leibholz, Derrick R. Meyer | 2002-09-10 |
| 6446143 | Methods and apparatus for minimizing the impact of excessive instruction retrieval | Rahul Razdan | 2002-09-03 |
| 6195748 | Apparatus for sampling instruction execution information in a processor pipeline | George Z. Chrysos, Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl +1 more | 2001-02-27 |
| 6163840 | Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline | George Z. Chrysos, Jeffrey Adgate Dean, James E. Hicks, Daniel Leibholz, Carl A. Waldspurger +1 more | 2000-12-19 |
| 6081887 | System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction | Simon C. Steely, Jr., Joel S. Emer | 2000-06-27 |
| 6000044 | Apparatus for randomly sampling instructions in a processor pipeline | George Z. Chrysos, Jeffrey Adgate Dean, James E. Hicks, Daniel Leibholz, Carl A. Waldspurger +1 more | 1999-12-07 |
| 5933860 | Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted | Joel S. Emer, Simon C. Steely, Jr. | 1999-08-03 |
| 5890201 | Content addressable memory having memory cells storing don't care states for address translation | Bruce Gieseke | 1999-03-30 |
| 5784709 | Translating buffer and method for translating addresses utilizing invalid and don't care states | Bruce Gieseke | 1998-07-21 |