Issued Patents All Time
Showing 25 most recent of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12210457 | Processor data cache with shared mid-level cache and low-level cache | Shubhendu Sekhar Mukherjee, David Asher, Srilatha Manne | 2025-01-28 |
| 12061729 | Secure low-latency chip-to-chip communication | Georgios Angelopoulos, Steven C. Barner | 2024-08-13 |
| 12019552 | Low latency inter-chip communication mechanism in a multi-chip processing system | Craig Barner, David Asher, Bradley Dobbie, Daniel Dever, Thomas F. Hummel +1 more | 2024-06-25 |
| 11868262 | Methods and systems for distributing memory requests | David Asher, Shubhendu Sekhar Mukherjee, Wilson P. Snyder, II, David A. Carlson, Jason D. Zebchuk +1 more | 2024-01-09 |
| 11709534 | Method and apparatus for managing global chip power on a multicore system on chip | David A. Carlson | 2023-07-25 |
| 11646971 | Limiting backpressure with bad actors | Nick Jamba, Victor Hart | 2023-05-09 |
| 11620223 | Low latency inter-chip communication mechanism in a multi-chip processing system | Craig Barner, David Asher, Bradley Dobbie, Daniel Dever, Thomas F. Hummel +1 more | 2023-04-04 |
| 11615027 | Methods and systems for distributing memory requests | David Asher, Shubhendu Sekhar Mukherjee, Wilson P. Snyder, II, David A. Carlson, Jason D. Zebchuk +1 more | 2023-03-28 |
| 11188466 | Methods and systems for distributing memory requests | David Asher, Shubhendu Sekhar Mukherjee, Wilson P. Snyder, II, David A. Carlson, Jason D. Zebchuk +1 more | 2021-11-30 |
| 11119929 | Low latency inter-chip communication mechanism in multi-chip processing system | Craig Barner, David Asher, Bradley Dobbie, Daniel Dever, Thomas F. Hummel +1 more | 2021-09-14 |
| 11093405 | Shared mid-level data cache | Shubhendu Sekhar Mukherjee, David Asher, Srilatha Manne | 2021-08-17 |
| 11095626 | Secure in-line received network packet processing | Shahe H. Krakirian | 2021-08-17 |
| 11038856 | Secure in-line network packet transmittal | — | 2021-06-15 |
| 10983576 | Method and apparatus for managing global chip power on a multicore system on chip | David A. Carlson | 2021-04-20 |
| 10872173 | Secure low-latency chip-to-chip communication | Georgios Angelopoulos, Steven C. Barner | 2020-12-22 |
| 10846239 | Managing translation lookaside buffer entries based on associativity and page size | Shubhendu Sekhar Mukherjee, Michael Bertone | 2020-11-24 |
| 10782896 | Local instruction ordering based on memory domains | Shubhendu Sekhar Mukherjee, Mike Bertone, Chris Comis, Bryan W. Chin | 2020-09-22 |
| 10732684 | Method and apparatus for managing global chip power on a multicore system on chip | David A. Carlson | 2020-08-04 |
| 10721172 | Limiting backpressure with bad actors | Nick Jamba, Victor Hart | 2020-07-21 |
| 10599577 | Admission control for memory access requests | Shubhendu Sekhar Mukherjee, Michael Bertone, David A. Carlson, Wilson P. Snyder, II | 2020-03-24 |
| 10599437 | Managing obscured branch prediction information | Wilson P. Snyder, II, Shubhendu Sekhar Mukherjee | 2020-03-24 |
| 10599430 | Managing lock and unlock operations using operation prediction | Shubhendu Sekhar Mukherjee, Isam Akkawi, David Asher, Michael Bertone, David A. Carlson +1 more | 2020-03-24 |
| 10592459 | Method and system for ordering I/O access in a multi-node environment | — | 2020-03-17 |
| 10558573 | Methods and systems for distributing memory requests | David Asher, Shubhendu Sekhar Mukherjee, Wilson P. Snyder, II, David A. Carlson, Jason D. Zebchuk +1 more | 2020-02-11 |
| 10540181 | Managing branch prediction information for different contexts | Shubhendu Sekhar Mukherjee, David William Kravitz, Edward J. McLellan, Rabin Sugumar | 2020-01-21 |