Issued Patents All Time
Showing 1–25 of 109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12293190 | Managing commit order for an external instruction relative to queued instructions | David A. Carlson, Michael Bertone | 2025-05-06 |
| 12210457 | Processor data cache with shared mid-level cache and low-level cache | David Asher, Richard E. Kessler, Srilatha Manne | 2025-01-28 |
| 12204904 | Dynamic designation of instructions as sensitive for constraining instruction execution | — | 2025-01-21 |
| 12145518 | Managing power in an integrated circuit for high-speed activation | William Chu | 2024-11-19 |
| 11886882 | Pipelines for secure multithread execution | — | 2024-01-30 |
| 11868262 | Methods and systems for distributing memory requests | Richard E. Kessler, David Asher, Wilson P. Snyder, II, David A. Carlson, Jason D. Zebchuk +1 more | 2024-01-09 |
| 11842198 | Managing out-of-order retirement of instructions based on received instructions indicating start or stop to out-of-order retirement | — | 2023-12-12 |
| 11822652 | Prime and probe attack mitigation | — | 2023-11-21 |
| 11766975 | Managing power in an integrated circuit for high-speed activation | William Chu | 2023-09-26 |
| 11748109 | System and method for implementing strong load ordering in a processor using a circular ordering ring | David A. Carlson, Wilson P. Snyder, II | 2023-09-05 |
| 11615027 | Methods and systems for distributing memory requests | Richard E. Kessler, David Asher, Wilson P. Snyder, II, David A. Carlson, Jason D. Zebchuk +1 more | 2023-03-28 |
| 11604873 | Noisy instructions for side-channel attack mitigation | — | 2023-03-14 |
| 11550590 | System and method for implementing strong load ordering in a processor using a circular ordering ring | David A. Carlson, Wilson P. Snyder, II | 2023-01-10 |
| 11513958 | Shared mid-level data cache | — | 2022-11-29 |
| 11507379 | Managing load and store instructions for memory barrier handling | Michael Bertone, David A. Carlson | 2022-11-22 |
| 11500779 | Vector prefetching for computing systems | — | 2022-11-15 |
| 11487874 | Prime and probe attack mitigation | — | 2022-11-01 |
| 11379379 | Differential cache block sizing for computing systems | David Asher, Thomas F. Hummel | 2022-07-05 |
| 11379372 | Managing prefetch lookahead distance based on memory access latency | — | 2022-07-05 |
| 11379368 | External way allocation circuitry for processor cores | Thomas F. Hummel | 2022-07-05 |
| 11372647 | Pipelines for secure multithread execution | — | 2022-06-28 |
| 11327759 | Managing low-level instructions and core interactions in multi-core processors | David A. Carlson, Michael Bertone, David Asher, Daniel Dever, Bradley Dobbie +1 more | 2022-05-10 |
| 11327890 | Partitioning in a processor cache | — | 2022-05-10 |
| 11307857 | Dynamic designation of instructions as sensitive for constraining multithreaded execution | — | 2022-04-19 |
| 11269644 | System and method for implementing strong load ordering in a processor using a circular ordering ring | David A. Carlson, Wilson P. Snyder, II | 2022-03-08 |