Issued Patents All Time
Showing 51–75 of 109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10223279 | Managing virtual-address caches for multiple memory page sizes | Michael Bertone, David A. Carlson | 2019-03-05 |
| 10216430 | Local ordering of instructions in a computing system | Richard E. Kessler, Mike Bertone, Chris Comis, Bryan W. Chin | 2019-02-26 |
| 10042778 | Collapsed address translation with multiple page sizes | Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis | 2018-08-07 |
| 10013357 | Managing memory access requests with prefetch for streams | David A. Carlson, Srilatha Manne | 2018-07-03 |
| 10013360 | Managing reuse information with multiple translation stages | — | 2018-07-03 |
| 9910776 | Instruction ordering for in-progress operations | Albert Ma, Mike Bertone | 2018-03-06 |
| 9870328 | Managing buffered communication between cores | David Asher, Bradley Dobbie, Thomas F. Hummel, Daniel Dever | 2018-01-16 |
| 9779028 | Managing translation invalidation | Mike Bertone | 2017-10-03 |
| 9772943 | Managing synonyms in virtual-address caches | — | 2017-09-26 |
| 9720773 | Managing reuse information in caches | — | 2017-08-01 |
| 9697137 | Filtering translation lookaside buffer invalidations | — | 2017-07-04 |
| 9684606 | Translation lookaside buffer invalidation suppression | Richard E. Kessler, Mike Bertone | 2017-06-20 |
| 9665505 | Managing buffered communication between sockets | David Asher, Bradley Dobbie, Thomas F. Hummel, Daniel Dever | 2017-05-30 |
| 9645941 | Collapsed address translation with multiple page sizes | Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis | 2017-05-09 |
| 9639476 | Merged TLB structure for multiple sequential address translations | Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler | 2017-05-02 |
| 9501425 | Translation lookaside buffer management | David Asher, Mike Bertone, Bradley Dobbie, Thomas F. Hummel | 2016-11-22 |
| 9471509 | Managing address-independent page attributes | — | 2016-10-18 |
| 9405702 | Caching TLB translations using a unified page table walker cache | Mike Bertone, Albert Ma | 2016-08-02 |
| 9390023 | Method and apparatus for conditional storing of data using a compare-and-swap based approach | Richard E. Kessler, David Asher, Michael Bertone, Wilson P. Snyder, II, John M. Perveiler +1 more | 2016-07-12 |
| 9323715 | Method and apparatus to represent a processor context with fewer bits | Michael Bertone, David A. Carlson | 2016-04-26 |
| 9268694 | Maintenance of cache and tags in a translation lookaside buffer | Wilson P. Snyder, II, Bryan W. Chin, Michael Bertone, Richard E. Kessler | 2016-02-23 |
| 9081688 | Obtaining data for redundant multithreading (RMT) execution | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +4 more | 2015-07-14 |
| 8914672 | General purpose hardware to replace faulty core components that may also provide additional processor functionality | Steven Raasch, Michael Powell, Arijit Biswas | 2014-12-16 |
| 8291394 | Method and apparatus for detecting transient faults via dynamic binary translation | George Reis, Robert Cohn | 2012-10-16 |
| 8171328 | State history storage for synchronizing redundant processors | Arijit Biswas, Paul Racunas, Steven Raasch | 2012-05-01 |