Issued Patents All Time
Showing 25 most recent of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11749663 | Device, method and system for providing a stacked arrangement of integrated circuit dies | Wilfred Gomes, Mark Bohr, Rajesh Kumar | 2023-09-05 |
| 11373987 | Device, method and system for providing a stacked arrangement of integrated circuit dies | Wilfred Gomes, Mark Bohr, Rajesh Kumar | 2022-06-28 |
| 11200176 | Dynamic partial power down of memory-side cache in a 2-level memory hierarchy | Raj K. Ramanujan, David J. Zimmerman | 2021-12-14 |
| 11132298 | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes | Raj K. Ramanujan, Rajat Agarwal | 2021-09-28 |
| 10795823 | Dynamic partial power down of memory-side cache in a 2-level memory hierarchy | Raj K. Ramanujan, David J. Zimmerman | 2020-10-06 |
| 10719443 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2020-07-21 |
| 10564986 | Methods and apparatus to suspend and resume computing systems | Michael A. Rothman, Vincent J. Zimmer, Barnes Cooper, Leena K. Puthiyedath | 2020-02-18 |
| 10469557 | QoS based binary translation and application streaming | Bharath Muthiah, William Rash, Martin G. Dixon, Scott D. Hahn, David B. Papworth | 2019-11-05 |
| 10365832 | Two-level system main memory | Eric J. Dahlen, Raj K. Ramanujan | 2019-07-30 |
| 10241912 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2019-03-26 |
| 10170165 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2019-01-01 |
| 10163468 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2018-12-25 |
| 10153012 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2018-12-11 |
| 10153011 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2018-12-11 |
| 10141033 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2018-11-27 |
| 10102888 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2018-10-16 |
| 10102126 | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes | Raj K. Ramanujan, Rajat Agarwal | 2018-10-16 |
| 10048868 | Replacement of a block with a compressed block to increase capacity of a memory-side cache | Alaa R. Alameldeen, Blaise Fanning, James J. Greensky | 2018-08-14 |
| 9786338 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2017-10-10 |
| 9703562 | Instruction emulation processors, methods, and systems | William C. Rash, Bret L. Toll, Scott D. Hahn | 2017-07-11 |
| 9690493 | Two-level system main memory | Eric J. Dahlen, Raj K. Ramanujan | 2017-06-27 |
| 9600416 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2017-03-21 |
| 9594648 | Controlling non-redundant execution in a redundant multithreading (RMT) processor | Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani +1 more | 2017-03-14 |
| 9525586 | QoS based binary translation and application streaming | Bharath Muthiah, William Rash, Martin G. Dixon, Scott Hayn, David B. Papworth | 2016-12-20 |
| 9424034 | Multiple register memory access instructions, processors, methods, and systems | Bret L. Toll, Ronak Singhal | 2016-08-23 |