Issued Patents All Time
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393421 | Techniques for decoupled access-execute near-memory processing | Berkin Akin | 2025-08-19 |
| 12271305 | Two-level main memory hierarchy management | Sai Prashanth Muralidhara, Rajat Agarwal, Wei-Pin Chen, Vivek Kozhikkottu | 2025-04-08 |
| 12106104 | Processor instructions for data compression and decompression | Zhe Wang, Christopher J. Hughes | 2024-10-01 |
| 12093573 | Low-complexity coverage-based compression | Amir Ali Radjai, Jason Van Dyken, Aditya Nagaraja, Joshua Underdown, James J. Greensky +1 more | 2024-09-17 |
| 12001346 | Device, method and system to supplement a skewed cache with a victim cache | Thomas Unterluggauer, Scott Constable, Fangfei Liu, Francis X. McKeen, Carlos V. Rozas +1 more | 2024-06-04 |
| 11853758 | Techniques for decoupled access-execute near-memory processing | Berkin Akin | 2023-12-26 |
| 11681533 | Restricted speculative execution mode to prevent observable side effects | Ron Gabor, Abhishek Basak, Fangfei Liu, Francis X. McKeen, Joseph Nuzman +3 more | 2023-06-20 |
| 11544093 | Virtual machine replication and migration | Zhe Wang, Andrew V. Anderson, Andrew M. Rudoff | 2023-01-03 |
| 11526448 | Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning | Zhe Wang, Yi Zou, Gordon L. King | 2022-12-13 |
| 11416248 | Method and system for efficient floating-point compression | Jaewoong Sim, Eriko Nurvitadhi, Deborah T. Marr | 2022-08-16 |
| 11188467 | Multi-level system memory with near memory capable of storing compressed cache lines | Israel Diamand, Sreenivas Subramoney, Supratik Majumder, Srinivas Santosh Kumar MADUGULA, Jayesh Gaur +2 more | 2021-11-30 |
| 11074188 | Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory | Zhe Wang, Lidia Warnes, Andy Rudoff, Muthukumar P. Swaminathan | 2021-07-27 |
| 10884927 | Cache architecture using way ID to reduce near memory traffic in a two-level memory system | Zhe Wang | 2021-01-05 |
| 10877890 | Providing dead-block prediction for determining whether to cache data in cache devices | Gino Chacon | 2020-12-29 |
| 10860244 | Method and apparatus for multi-level memory early page demotion | Binh Pham, Christopher B. Wilkerson, Zeshan A. Chishti, Zhe Wang | 2020-12-08 |
| 10802883 | Method, system, and device for near-memory processing with cores of a plurality of sizes | Berkin Akin | 2020-10-13 |
| 10691602 | Adaptive granularity for reducing cache coherence overhead | Gino Chacon | 2020-06-23 |
| 10452312 | Apparatus, system, and method to determine a demarcation voltage to use to read a non-volatile memory | Zhe Wang, Zeshan A. Chishti, Muthukumar P. Swaminathan, Kunal A. Khochare, Jason A. Gayman | 2019-10-22 |
| 10417135 | Near memory miss prediction to reduce memory access latency | Zhe Wang, Zeshan A. Chishti, Rajat Agarwal | 2019-09-17 |
| 10261901 | Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory | Zhe Wang, Christopher B. Wilkerson, Zeshan A. Chishti, Seth H. Pugsley, Shih-Lien Linus Lu | 2019-04-16 |
| 10108549 | Method and apparatus for pre-fetching data in a system having a multi-level system memory | Zhe Wang, Christopher B. Wilkerson, Zeshan A. Chishti, Seth H. Pugsley, Shih-Lien Linus Lu | 2018-10-23 |
| 10048868 | Replacement of a block with a compressed block to increase capacity of a memory-side cache | Glenn J. Hinton, Blaise Fanning, James J. Greensky | 2018-08-14 |
| 9921961 | Multi-level memory management | Christopher B. Wilkerson, Zhe Wang, Zeshan A. Chishti | 2018-03-20 |
| 9921972 | Method and apparatus for implementing a heterogeneous memory subsystem | Christopher B. Wilkerson, Zeshan A. Chishti, Jaewoong Sim | 2018-03-20 |
| 9703708 | System and method for thread scheduling on reconfigurable processor cores | Christopher B. Wilkerson, Eugene Gorbatov, Zeshan A. Chishti | 2017-07-11 |