Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393421 | Techniques for decoupled access-execute near-memory processing | Alaa R. Alameldeen | 2025-08-19 |
| 11853758 | Techniques for decoupled access-execute near-memory processing | Alaa R. Alameldeen | 2023-12-26 |
| 11720362 | Apparatus and method for a tensor permutation engine | — | 2023-08-08 |
| 11593623 | Spiking neural network accelerator using external memory | Seth H. Pugsley | 2023-02-28 |
| 11366998 | Neuromorphic accelerator multitasking | Seth H. Pugsley | 2022-06-21 |
| 11354568 | In-memory spiking neural networks for memory array architectures | Seth H. Pugsley | 2022-06-07 |
| 11030108 | System, apparatus and method for selective enabling of locality-based instruction handling | Rajat Agarwal, Jong Soo Park, Christopher J. Hughes, Chiachen Chou | 2021-06-08 |
| 10908906 | Apparatus and method for a tensor permutation engine | — | 2021-02-02 |
| 10802883 | Method, system, and device for near-memory processing with cores of a plurality of sizes | Alaa R. Alameldeen | 2020-10-13 |
| 10409727 | System, apparatus and method for selective enabling of locality-based instruction handling | Rajat Agarwal, Jong Soo Park, Christopher J. Hughes, Chiachen Chou | 2019-09-10 |
| 10402336 | System, apparatus and method for overriding of non-locality-based instruction handling | Rajat Agarwal, Jong Soo Park, Christopher J. Hughes | 2019-09-03 |
| 10068636 | Apparatuses and methods for accessing and scheduling between a plurality of row buffers | Shigeki Tomishima | 2018-09-04 |