AA

Alaa R. Alameldeen

IN Intel: 39 patents #894 of 30,777Top 3%
WARF: 1 patents #1,912 of 4,123Top 50%
📍 Hillsboro, OR: #96 of 2,365 inventorsTop 5%
🗺 Oregon: #941 of 28,073 inventorsTop 4%
Overall (All Time): #77,901 of 4,157,543Top 2%
40
Patents All Time

Issued Patents All Time

Showing 26–40 of 40 patents

Patent #TitleCo-InventorsDate
9583182 Multi-level memory management Christopher B. Wilkerson, Zhe Wang, Zeshan A. Chishti 2017-02-28
9472248 Method and apparatus for implementing a heterogeneous memory subsystem Christopher B. Wilkerson, Zeshan A. Chishti, Jaewoong Sim 2016-10-18
9417879 Systems and methods for managing reconfigurable processor cores Christopher B. Wilkerson, Eugene Gorbatov, Zeshan A. Chishti 2016-08-16
9311085 Compiler assisted low power and high performance load handling based on load types Tingting Sha, Chris Wilkerson, Herbert Hum 2016-04-12
9292449 Cache memory data compression and decompression Niranjan L. Cooray, Jayesh Gaur, Steven D. Pudar, Manuel A. Aguilar Arreola, Margareth E. Marrugo +1 more 2016-03-22
9251096 Data compression in processor caches Sreenivas Subramoney, Jayesh Gaur 2016-02-02
9223710 Read-write partitioning of cache memory Christopher B. Wilkerson, Samira M. Khan 2015-12-29
8966345 Selective error correction in memory to reduce power consumption Christopher B. Wilkerson, Shih-Lien Linus Lu 2015-02-24
8868836 Reducing minimum operating voltage through hybrid cache design Muhammad M. Khellah, Christopher B. Wilkerson, Bibiche M. Geuskens, Tanay Karnik, Vivek K. De +1 more 2014-10-21
8806285 Dynamically allocatable memory error mitigation Ilya Wagner, Zeshan A. Chishti, Wei Wu, Christopher B. Wilkerson 2014-08-12
8719502 Adaptive self-repairing cache Christopher B. Wilkerson, Jaydeep P. Kulkarni 2014-05-06
8640005 Method and apparatus for using cache memory in a system that supports a low power state Christopher B. Wilkerson, Zeshan A. Chishti, Dinesh Somasekhar, Wei Wu, Shih-Lien Linus Lu 2014-01-28
8276142 Hardware support for thread scheduling on multi-core processors Zeshan A. Chishti 2012-09-25
8245111 Performing multi-bit error correction on a cache line Zeshan A. Chishti, Chris Wilkerson, Wei Wu, Dinesh Somasekhar, Muhammad M. Khellah +1 more 2012-08-14
7412564 Adaptive cache compression system David A. Wood 2008-08-12