| 12430135 |
Device, method, and system to facilitate improved bandwidth of a branch prediction unit |
Sumeet Bandishte, Franck Sala, Alexey Y. Sivtsov, Jared W. Stark, IV, Lihu Rappoport +1 more |
2025-09-30 |
|
| 12182018 |
Instruction and micro-architecture support for decompression on core |
Adarsh Chauhan, Vinodh Gopal, Vedvyas Shanbhogue, Sreenivas Subramoney, Wajdi K. Feghali |
2024-12-31 |
$16,542,000 |
| 12130738 |
Compressed cache memory with decompress on fault |
Vedvyas Shanbhogue, Wajdi K. Feghali, Vinodh Gopal, Utkarsh Y. Kakaiya |
2024-10-29 |
$18,861,000 |
| 12086591 |
Device, method and system to predict an address collision by a load and a store |
Sudhanshu Shukla, Stanislav Shwartsman, Pavel I. Kryukov |
2024-09-10 |
$16,964,000 |
| 12028094 |
Application programming interface for fine grained low latency decompression within processor core |
Adarsh Chauhan, Vinodh Gopal, Vedvyas Shanbhogue, Sreenivas Subramoney, Wajdi K. Feghali |
2024-07-02 |
$27,114,000 |
| 12020033 |
Apparatus and method for hardware-based memoization of function calls to reduce instruction execution |
Niranjan Soundararajan, Sreenivas Subramoney, S R Swamy Saranam Chongala |
2024-06-25 |
$22,163,000 |
| 11972126 |
Data relocation for inline metadata |
David M. Durham, Michael LeMay, Sergej Deutsch, Joydeep Rakshit, Anant Vithal Nori +1 more |
2024-04-30 |
$26,151,000 |
| 11656971 |
Technology for dynamically tuning processor features |
Adarsh Chauhan, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz +1 more |
2023-05-23 |
$11,397,000 |
| 11645078 |
Detecting a dynamic control flow re-convergence point for conditional branches in hardware |
Adarsh Chauhan, Franck Sala, Zeev Sperber, Lihu Rappoport, Adi Yoaz +1 more |
2023-05-09 |
$19,706,000 |
| 11575504 |
Cryptographic computing engine for memory load and store units of a microarchitecture pipeline |
David M. Durham, Michael LeMay, Michael E. Kounavis, Santosh Ghosh, Sergej Deutsch +3 more |
2023-02-07 |
$11,877,000 |
| 11256599 |
Technology for dynamically tuning processor features |
Adarsh Chauhan, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz +1 more |
2022-02-22 |
$16,582,000 |
| 11188467 |
Multi-level system memory with near memory capable of storing compressed cache lines |
Israel Diamand, Alaa R. Alameldeen, Sreenivas Subramoney, Supratik Majumder, Srinivas Santosh Kumar MADUGULA +2 more |
2021-11-30 |
$30,212,000 |
| 11043256 |
High bandwidth destructive read embedded memory |
Kaushik Vaidyanathan, Huichu Liu, Tanay Karnik, Sreenivas Subramoney, Sudhanshu Shukla |
2021-06-22 |
$40,504,000 |
| 10956327 |
Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP) |
Adithya NALLAN CHAKRAVARTHI, Anant Vithal Nori, Sreenivas Subramoney |
2021-03-23 |
$29,278,000 |
| 10915421 |
Technology for dynamically tuning processor features |
Adarsh Chauhan, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz +1 more |
2021-02-09 |
$44,388,000 |
| 10866902 |
Memory aware reordered source |
Ishwar Bhati, Udit Dhawan, Sreenivas Subramoney |
2020-12-15 |
$39,832,000 |
| 10846093 |
System, apparatus and method for focused data value prediction to accelerate focused instructions |
Sumeet Bandishte, Sreenivas Subramoney, Hong Wang |
2020-11-24 |
$25,522,000 |
| 10776270 |
Memory-efficient last level cache architecture |
Ayan Mandal, Anant Vithal Nori, Sreenivas Subramoney |
2020-09-15 |
$34,212,000 |
| 10754655 |
Automatic predication of hard-to-predict convergent branches |
Adarsh Chauhan, Hong Wang, Zeev Sperber, Sumeet Bandishte, Lihu Rappoport +4 more |
2020-08-25 |
$27,661,000 |
| 10719355 |
Criticality based port scheduling |
Pooja Roy, Sreenivas Subramoney, Zeev Sperber, Alexandr Titov, Lihu Rappoport +5 more |
2020-07-21 |
$33,796,000 |
| 10496413 |
Efficient hardware-based extraction of program instructions for critical paths |
Pooja Roy, Sreenivas Subramoney, Hong Wang, Ronak Singhal |
2019-12-03 |
$19,496,000 |
| 10331582 |
Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time |
Ishwar Bhati, Huichu Liu, Kunal Kishore Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney +3 more |
2019-06-25 |
$17,766,000 |
| 10268600 |
System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor |
Sreenivas Subramoney, Sanjay Ganapathy |
2019-04-23 |
$25,127,000 |
| 10176099 |
Using data pattern to mark cache lines as invalid |
Supratik Majumder, Zvika Greenfield, Israel Diamand |
2019-01-08 |
$28,117,000 |
| 10162756 |
Memory-efficient last level cache architecture |
Ayan Mandal, Anant Vithal Nori, Sreenivas Subramoney |
2018-12-25 |
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